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From: gcc-patches-ow...@gcc.gnu.org <gcc-patches-ow...@gcc.gnu.org> on behalf of Tamar Christina <tamar.christ...@arm.com> Sent: Thursday, August 18, 2016 10:15:12 AM To: GCC Patches Cc: James Greenhalgh; Richard Earnshaw; Marcus Shawcroft; nd Subject: [PATCH][Aarch64][gcc] Fix vld2/3/4 on big endian systems Hi all, This fixes a bug in the vector load functions in which they load the vector in the wrong order for big endian systems. This patch flips the order conditionally in the vec_concats. No testcase given because plenty of existing tests for vld functions. Ran regression tests on aarch64_be-none-elf and aarch64-none-elf. Vldx tests now pass on aarch64_be-none-elf and no regressions on both. Ok for trunk? I do not have commit rights so if ok can someone apply it for me? Thanks, Tamar gcc/ 2016-08-16 Tamar Christina <tamar.christ...@arm.com> * gcc/config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg_le): New. (aarch64_ld2<mode>_dreg_be): New. (aarch64_ld2<mode>_dreg): Removed. (aarch64_ld3<mode>_dreg_le): New. (aarch64_ld3<mode>_dreg_be): New. (aarch64_ld3<mode>_dreg): Removed. (aarch64_ld4<mode>_dreg_le): New. (aarch64_ld4<mode>_dreg_be): New. (aarch64_ld4<mode>_dreg): Removed. (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Wrapper around _le, _be.
