On Tue, May 17, 2016 at 3:31 PM, Matthew Wahab <matthew.wa...@foss.arm.com> wrote: > The ACLE specifies a number of intrinsics for manipulating vectors > holding values in most of the integer and floating point type. These > include 16-bit integer types but not 16-bit floating point even though > the same instruction is used for both. > > A future version of the ACLE extends the data processing intrinscs to > the 16-bit floating point types, making the intrinsics available > under the same conditions as the ARM __fp16 type. > > This patch adds the new intrinsics: > vbsl_f16, vbslq_f16, vdup_n_f16, vdupq_n_f16, vdup_lane_f16, > vdupq_lane_f16, vext_f16, vextq_f16, vmov_n_f16, vmovq_n_f16, > vrev64_f16, vrev64q_f16, vtrn_f16, vtrnq_f16, vuzp_f16, vuzpq_f16, > vzip_f16, vzipq_f16. > > This patch also updates the advsimd-intrinsics testsuite to test the f16 > variants for ARM targets. These intrinsics are only implemented in the > ARM target so the tests are disabled for AArch64 using an extra > condition on a new convenience macro FP16_SUPPORTED. This patch also > disables, for the ARM target, the testsuite defined macro vdup_n_f16 as > it is no longer needed. > > Tested the series for arm-none-linux-gnueabihf with native bootstrap and > make check and for arm-none-eabi and armeb-none-eabi with make check on > an ARMv8.2-A emulator. Also tested for aarch64-none-elf with the > advsimd-intrinsics testsuite using an ARMv8.2-A emulator. > > Ok for trunk? > Matthew > > 2016-05-17 Matthew Wahab <matthew.wa...@arm.com> > > * config/arm/arm.c (arm_evpc_neon_vuzp): Add support for V8HF and > V4HF modes. > (arm_evpc_neon_vzip): Likewise. > (arm_evpc_neon_vrev): Likewise. > (arm_evpc_neon_vtrn): Likewise. > (arm_evpc_neon_vext): Likewise. > * config/arm/arm_neon.h (vbsl_f16): New. > (vbslq_f16): New. > (vdup_n_f16): New. > (vdupq_n_f16): New. > (vdup_lane_f16): New. > (vdupq_lane_f16): New. > (vext_f16): New. > (vextq_f16): New. > (vmov_n_f16): New. > (vmovq_n_f16): New. > (vrev64_f16): New. > (vrev64q_f16): New. > (vtrn_f16): New. > (vtrnq_f16): New. > (vuzp_f16): New. > (vuzpq_f16): New. > (vzip_f16): New. > (vzipq_f16): New. > * config/arm/arm_neon_buillins.def (vdup_n): New (v8hf, v4hf > variants). > (vdup_lane): New (v8hf, v4hf variants). > (vext): New (v8hf, v4hf variants). > (vbsl): New (v8hf, v4hf variants). > * config/arm/iterators.md (VDQWH): New. > (VH): New. > (V_double_vector_mode): Add V8HF and V4HF. Fix white-space. > (Scalar_mul_8_16): Fix white-space. > (Is_d_reg): Add V4HF and V8HF. > * config/arm/neon.md (neon_vdup_lane<mode>_internal): New. > (neon_vdup_lane<mode>): New. > (neon_vtrn<mode>_internal): Replace VDQW with VDQWH. > (*neon_vtrn<mode>_insn): Likewise. > (neon_vzip<mode>_internal): Likewise. Also fix white-space. > (*neon_vzip<mode>_insn): Likewise > (neon_vuzp<mode>_internal): Likewise. > (*neon_vuzp<mode>_insn): Likewise > * config/arm/vec-common.md (vec_perm_const<mode>): New. > > testsuite/ > 2016-05-17 Matthew Wahab <matthew.wa...@arm.com> > > * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h > (FP16_SUPPORTED): New > (vdup_n_f16): Disable for non-AArch64 targets. > * gcc.target/aarch64/advsimd-intrinsics/vbsl.c: Add __fp16 tests, > conditional on FP16_SUPPORTED. > * gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vext.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Add support > for testing __fp16. > * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: Add __fp16 tests, > conditional on FP16_SUPPORTED. > * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise. >
OK. Ramana
