On Thu, Jun 23, 2016 at 06:37:15PM -0400, Michael Meissner wrote:
> PowerPC ISA 3.0 adds new instructions (LXSIHZX, LXSIBZX, STXSIHX, and STXSIBX)
> that allow you to load and zero extend byte and half word values from memory
> and to store them back.
Okay for trunk with fixes below; okay for 6 later.
> @@ -872,7 +878,6 @@ (define_insn_and_split "*zero_extendsi<m
> (set_attr "dot" "yes")
> (set_attr "length" "4,8")])
>
> -
> (define_insn "extendqi<mode>2"
> [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
> (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
Unrelated whitespace change, please don't.
> @@ -5188,6 +5193,107 @@ (define_insn_and_split "*floatunssidf2_i
> [(set_attr "length" "20")
> (set_attr "type" "fp")])
>
> +;; ISA 3.0 adds instructions lxsi[bh]zx to directly load QImode and HImode to
> +;; vector registers. At the moment, QI/HImode are not allowed in floating
> +;; point or vector registers, so we use UNSPEC's to use the load byte and
> +;; half-word instructions.
> +
> +(define_expand "float<QHI:mode><FP_ISA3:mode>2"
> + [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "")
> + (float:FP_ISA3
> + (match_operand:QHI 1 "input_operand" "")))
> + (clobber (match_scratch:DI 2 ""))
> + (clobber (match_scratch:DI 3 ""))])]
Drop the "" please.
> + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
> +{
> + if (MEM_P (operands[1]))
> + operands[1] = rs6000_address_for_fpconvert (operands[1]);
That function should get a better name, it's not used soletly for fpconvert
anymore. I'm not asking you to do this now, it should be a separate patch
anyway ;-)
Thanks,
Segher
