On 10/06/16 15:30, Matthew Wahab wrote:
> On 10/06/16 15:22, Christophe Lyon wrote:
>> On 10 June 2016 at 15:56, Matthew Wahab <matthew.wa...@foss.arm.com> wrote:
>>> On 10/06/16 09:32, Christophe Lyon wrote:
>>>>
>>>> On 9 June 2016 at 17:21, Matthew Wahab <matthew.wa...@foss.arm.com> wrote:
>>>>>
>>>> It's an improvement, but I'm still seeing a few problems with this patch:
>>>> the vfp* tests are still failing in some of the configurations I test,
>>>> because
>>>> * you force dg-options that contains -mfloat-abi=hard,
>>>> * you check effective-target arm_neon_fp16_hw
>>>> * but you don't call dg-add-options arm_neon_fp16
>>>>
> I understand now. I still think it would be better to use a list of
> require-effective-targets so I'll try that first and use the arm_neon_fp16
> options if that doesn't work.
>
Sorry for the delay. I've added effective-target requirements to the
tests to check for hard-fp and for VFP (i.e. non-neon) FP16 support. The
directives for the VFP FP16 support are new. I've split them out to a
separate patch, both patches are attached.
The first patch adds:
- effective-target keywords arm_fp16_ok and arm_fp16_hw to check for
compiler and hardware support for FP16.
- add-options features arm_fp16_ieee and arm_fp16_alternative, to
enable FP16 IEEE format and FP16 ARM Alternative format support
Note that the existing add-options feature arm_fp16 enables the default
FP16 format (fp16-format=none).
The second patch updates the tests to use these directives. It also
reworks gcc.target/arm/fp16-aapcs-1.c test is also reworked to focus on
argument passing and return values adds a softfp variant as
fp16-aapcs-2.c.
As before, checked for arm-none-eabi with cross-compiled check-gcc and
arm-linux-gnueabihf with native make check. I also ran the tests for
cross-compiled arm-none-eabi with -mcpu=Cortex-M3.
Ok for trunk?
Matthew
PATCH 1/2 ChangeLog
gcc/
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* doc/sourcebuild.texi (Effective-Target keywords): Add entries
for arm_fp16_ok and arm_fp16_hw.
(Add Options): Add entries for arm_fp16, arm_fp16_ieee and
arm_fp16_alternative.
testsuite/
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* lib/target-supports.exp (add_options_for arm_fp16): Reword
comment.
(add_options_for_arm_fp16_ieee): New.
(add_options_for_arm_fp16_alternative): New.
(check_effective_target_arm_fp16_ok_nocache): Add to comment. Fix a
long-line.
(check_effective_target_arm_fp16_hw): New.
PATCH 2/2 ChangeLog
testsuite/
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* testsuite/gcc.target/arm/aapcs/neon-vect10.c: Require
-mfloat-ab=hard. Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
* testsuite/gcc.target/arm/aapcs/neon-vect9.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp18.c: Likewise. Also add
options for ARM FP16 IEEE format.
* testsuite/gcc.target/arm/aapcs/vfp19.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp20.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp21.c: Likewise.
* testsuite/gcc.target/arm/fp16-aapcs-1.c: Require
-mfloat-ab=hard. Also simplify the test.
* testsuite/gcc.target/arm/fp16-aapcs-2.c: New.
>From ff46f8397b2ae4ffe3be0027849aa8ff63e9ab9b Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wa...@arm.com>
Date: Mon, 13 Jun 2016 13:30:13 +0100
Subject: [PATCH 1/2] [Testsuite] Selectors and options directives for ARM VFP
FP16 support.
To support FP16 VFP tests for the ARM backend, this patch adds:
- effective-target keywords arm_fp16_ok and arm_fp16_hw to check for
compiler and hardware support for FP16.
- add-options features arm_fp16_ieee and arm_fp16_alternative, to
enable FP16 IEEE format and FP16 ARM Alternative format support
Note that the existing add-options feature arm_fp16 enables the default
FP16 format (fp16-format=none).
gcc/
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* doc/sourcebuild.texi (Effective-Target keywords): Add entries
for arm_fp16_ok and arm_fp16_hw.
(Add Options): Add entries for arm_fp16, arm_fp16_ieee and
arm_fp16_alternative.
testsuite/
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* lib/target-supports.exp (add_options_for arm_fp16): Reword
comment.
(add_options_for_arm_fp16_ieee): New.
(add_options_for_arm_fp16_alternative): New.
(effective_target_arm_fp16_ok_nocache): Add to comment. Fix a
long-line.
(effective_target_arm_fp16_hw): New.
---
gcc/doc/sourcebuild.texi | 32 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 58 ++++++++++++++++++++++++++++++++---
2 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 95a781d..23d3c3f 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1555,6 +1555,16 @@ options. Some multilibs may be incompatible with these options.
ARM Target supports @code{-mfpu=neon-vfpv4 -mfloat-abi=softfp} or compatible
options. Some multilibs may be incompatible with these options.
+@item arm_fp16_ok
+@anchor{arm_fp16_ok}
+Target supports options to generate VFP half-precision floating-point
+instructions. Some multilibs may be incompatible with these
+options. This test is valid for ARM only.
+
+@item arm_fp16_hw
+Target supports executing VFP half-precision floating-point
+instructions. This test is valid for ARM only.
+
@item arm_neon_fp16_ok
@anchor{arm_neon_fp16_ok}
ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
@@ -2075,6 +2085,28 @@ NEON support. Only ARM targets support this feature, and only then
in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target
keyword}.
+@item arm_fp16
+VFP half-precision floating point support. This does not select the
+FP16 format; for that, use @ref{arm_fp16_ieee,,arm_fp16_ieee} or
+@ref{arm_fp16_alternative,,arm_fp16_alternative} instead. This
+feature is only supported by ARM targets and then only in certain
+modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
+keyword}.
+
+@item arm_fp16_ieee
+@anchor{arm_fp16_ieee}
+ARM IEEE 754-2008 format VFP half-precision floating point support.
+This feature is only supported by ARM targets and then only in certain
+modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
+keyword}.
+
+@item arm_fp16_alternative
+@anchor{arm_fp16_alternative}
+ARM Alternative format VFP half-precision floating point support.
+This feature is only supported by ARM targets and then only in certain
+modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
+keyword}.
+
@item arm_neon_fp16
NEON and half-precision floating point support. Only ARM targets
support this feature, and only then in certain modes; see
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 2b80f6e..d181809 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3184,9 +3184,9 @@ proc check_effective_target_arm_neonv2_ok { } {
check_effective_target_arm_neonv2_ok_nocache]
}
-# Add the options needed for NEON. We need either -mfloat-abi=softfp
-# or -mfloat-abi=hard, but if one is already specified by the
-# multilib, use it.
+# Add the options needed for VFP FP16 support. We need either
+# -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
+# the multilib, use it.
proc add_options_for_arm_fp16 { flags } {
if { ! [check_effective_target_arm_fp16_ok] } {
@@ -3196,9 +3196,32 @@ proc add_options_for_arm_fp16 { flags } {
return "$flags $et_arm_fp16_flags"
}
+# Add the options needed to enable support for IEEE format
+# half-precision support. This is valid for ARM targets.
+
+proc add_options_for_arm_fp16_ieee { flags } {
+ if { ! [check_effective_target_arm_fp16_ok] } {
+ return "$flags"
+ }
+ global et_arm_fp16_flags
+ return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
+}
+
+# Add the options needed to enable support for ARM Alternative format
+# half-precision support. This is valid for ARM targets.
+
+proc add_options_for_arm_fp16_alternative { flags } {
+ if { ! [check_effective_target_arm_fp16_ok] } {
+ return "$flags"
+ }
+ global et_arm_fp16_flags
+ return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
+}
+
# Return 1 if this is an ARM target that can support a VFP fp16 variant.
# Skip multilibs that are incompatible with these options and set
-# et_arm_fp16_flags to the best options to add.
+# et_arm_fp16_flags to the best options to add. This test is valid for
+# ARM only.
proc check_effective_target_arm_fp16_ok_nocache { } {
global et_arm_fp16_flags
@@ -3206,7 +3229,10 @@ proc check_effective_target_arm_fp16_ok_nocache { } {
if { ! [check_effective_target_arm32] } {
return 0;
}
- if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" "-mfpu=*fpv[1-9][0-9]*" } ]] {
+ if [check-flags \
+ [list "" { *-*-* } { "-mfpu=*" } \
+ { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
+ "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
# Multilib flags would override -mfpu.
return 0
}
@@ -3242,6 +3268,28 @@ proc check_effective_target_arm_fp16_ok { } {
check_effective_target_arm_fp16_ok_nocache]
}
+# Return 1 if the target supports executing VFP FP16 instructions, 0
+# otherwise. This test is valid for ARM only.
+
+proc check_effective_target_arm_fp16_hw { } {
+ if {! [check_effective_target_arm_fp16_ok] } {
+ return 0
+ }
+ global et_arm_fp16_flags
+ check_runtime_nocache arm_fp16_hw {
+ int
+ main (int argc, char **argv)
+ {
+ __fp16 a = 1.0;
+ float r;
+ asm ("vcvtb.f32.f16 %0, %1"
+ : "=w" (r) : "w" (a)
+ : /* No clobbers. */);
+ return (r == 1.0) ? 0 : 1;
+ }
+ } "$et_arm_fp16_flags -mfp16-format=ieee"
+}
+
# Creates a series of routines that return 1 if the given architecture
# can be selected and a routine to give the flags to select that architecture
# Note: Extra flags may be added to disable options from newer compilers
--
2.1.4
>From 770e71af35f6e7f4e78409121e50ffb05a013645 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wa...@arm.com>
Date: Wed, 15 Jun 2016 09:20:31 +0100
Subject: [PATCH 2/2] [ARM] Fix, add tests for FP16 aapcs.
2016-06-27 Matthew Wahab <matthew.wa...@arm.com>
* testsuite/gcc.target/arm/aapcs/neon-vect10.c: Require
-mfloat-ab=hard. Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
* testsuite/gcc.target/arm/aapcs/neon-vect9.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp18.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp19.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp20.c: Likewise.
* testsuite/gcc.target/arm/aapcs/vfp21.c: Likewise.
* testsuite/gcc.target/arm/fp16-aapcs-1.c: Require
-mfloat-ab=hard. Also simplify the test.
* testsuite/gcc.target/arm/fp16-aapcs-2.c: New.
---
gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c | 3 ++-
gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c | 3 ++-
gcc/testsuite/gcc.target/arm/aapcs/vfp18.c | 7 ++++---
gcc/testsuite/gcc.target/arm/aapcs/vfp19.c | 9 +++++----
gcc/testsuite/gcc.target/arm/aapcs/vfp20.c | 9 +++++----
gcc/testsuite/gcc.target/arm/aapcs/vfp21.c | 9 +++++----
gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c | 24 ++++++++++++++----------
gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c | 21 +++++++++++++++++++++
8 files changed, 58 insertions(+), 27 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
index 680a3b5..788079b 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
@@ -1,7 +1,8 @@
/* Test AAPCS layout (VFP variant for Neon types) */
/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_fp16_hw } */
/* { dg-add-options arm_neon_fp16 } */
#ifndef IN_FRAMEWORK
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
index fc2b13b..b42fdd2 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
@@ -1,7 +1,8 @@
/* Test AAPCS layout (VFP variant for Neon types) */
/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_fp16_hw } */
/* { dg-add-options arm_neon_fp16 } */
#ifndef IN_FRAMEWORK
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
index 225e9ce..0745a82 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant) */
/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_fp16_hw } */
+/* { dg-add-options arm_fp16_ieee } */
#ifndef IN_FRAMEWORK
#define VFP
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
index 8928b15..950c1f6 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant) */
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_fp16_hw } */
+/* { dg-add-options arm_fp16_ieee } */
#ifndef IN_FRAMEWORK
#define VFP
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
index 61f0704..f898d4c 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant) */
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_fp16_hw } */
+/* { dg-add-options arm_fp16_ieee } */
#ifndef IN_FRAMEWORK
#define VFP
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
index 15dff7d..48bb598 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant) */
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_fp16_hw } */
+/* { dg-add-options arm_fp16_ieee } */
#ifndef IN_FRAMEWORK
#define VFP
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
index 5eab3e2..9bf3fc0 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
@@ -1,17 +1,21 @@
/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
/* { dg-require-effective-target arm_fp16_ok } */
-/* { dg-options "-mfp16-format=ieee -O2" } */
-/* { dg-add-options arm_fp16 } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_fp16_ieee } */
-/* Test __fp16 arguments and return value in registers. */
+/* Test __fp16 arguments and return value in registers (hard-float). */
-__fp16 F (__fp16 a, __fp16 b, __fp16 c)
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
{
- if (a == b)
- return c;
- return a;
+ swap (b, a);
+ return c;
}
-/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s0} 1 } } */
-/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s1} 1 } } */
-/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } } */
+/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } } */
+/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
new file mode 100644
index 0000000..4753e36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_fp16_ok } */
+/* { dg-options "-mfloat-abi=softfp -O2" } */
+/* { dg-add-options arm_fp16_ieee } */
+/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
+
+/* Test __fp16 arguments and return value in registers (softfp). */
+
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
+{
+ swap (b, a);
+ return c;
+}
+
+/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */
+/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } } */
+/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */
--
2.1.4
