Support for using the half-precision floating point operations added by
the ARMv8.2-A FP16 extension is based on the macros and intrinsics added
to the ACLE for the extension.
This patch adds executable tests for the ACLE scalar (floating point)
intrinsics to the advsimd-intrinsics testsuite. The tests were written
by Jiong Wang.
In some tests, there are unavoidable differences in precision when
calculating the actual and the expected results of an FP16 operation. A
new support function CHECK_FP_BIAS is used so that these tests can check
for an acceptable margin of error. In these tests, the tolerance is
given as the absolute integer difference between the bitvectors of the
expected and the actual results.
Tested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and for arm-none-eabi and armeb-none-eabi with make check on
an ARMv8.2-A emulator. Also tested for aarch64-none-elf with the
advsimd-intrinsics testsuite using an ARMv8.2-A emulator.
Ok for trunk?
Matthew
testsuite/
2016-05-17 Jiong Wang <jiong.w...@arm.com>
Matthew Wahab <matthew.wa...@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(CHECK_FP_BIAS): New.
* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.
>From fe243d41337fcce0c93a8ce1df68921c680bcfe8 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wa...@arm.com>
Date: Thu, 7 Apr 2016 15:40:52 +0100
Subject: [PATCH 16/17] [PATCH 16/17][ARM] Add tests for VFP FP16 ACLE
instrinsics.
testsuite/
2016-05-17 Jiong Wang <jiong.w...@arm.com>
Matthew Wahab <matthew.wa...@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(CHECK_FP_BIAS): New.
* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.
---
.../aarch64/advsimd-intrinsics/arm-neon-ref.h | 40 +++++++++++++
.../aarch64/advsimd-intrinsics/vabsh_f16_1.c | 41 +++++++++++++
.../aarch64/advsimd-intrinsics/vaddh_f16_1.c | 42 +++++++++++++
.../aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c | 49 +++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c | 49 +++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c | 57 ++++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c | 56 ++++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c | 54 +++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c | 54 +++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c | 50 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vdivh_f16_1.c | 52 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vfmah_f16_1.c | 69 ++++++++++++++++++++++
.../aarch64/advsimd-intrinsics/vfmsh_f16_1.c | 69 ++++++++++++++++++++++
.../aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vminnmh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vmulh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vnegh_f16_1.c | 63 ++++++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndah_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndih_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndmh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndnh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndph_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vrndxh_f16_1.c | 51 ++++++++++++++++
.../aarch64/advsimd-intrinsics/vsqrth_f16_1.c | 58 ++++++++++++++++++
.../aarch64/advsimd-intrinsics/vsubh_f16_1.c | 42 +++++++++++++
35 files changed, 1805 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 001e320..0585b7e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -122,6 +122,46 @@ extern size_t strlen(const char *);
fprintf(stderr, "CHECKED %s\n", MSG); \
}
+/* Floating-point variant tolerate minor diffs. */
+#define CHECK_FP_BIAS(MSG, T, W, N, FMT, EXPECTED, COMMENT, BIAS) \
+ { \
+ int i; \
+ uint##W##_t op_max; \
+ uint##W##_t op_min; \
+ for (i=0; i<N ; i++) \
+ { \
+ union fp_operand \
+ { \
+ uint##W##_t i; \
+ float##W##_t f; \
+ } tmp_res, tmp_exp; \
+ tmp_res.f = VECT_VAR (result, T, W, N)[i]; \
+ tmp_exp.i = VECT_VAR (EXPECTED, h##T, W, N)[i]; \
+ op_max = tmp_exp.i; \
+ op_min = tmp_res.i; \
+ if (tmp_res.i > tmp_exp.i) \
+ { \
+ op_max = tmp_res.i; \
+ op_min = tmp_exp.i; \
+ } \
+ if ((op_max - op_min) > BIAS) \
+ { \
+ fprintf (stderr, \
+ "ERROR in %s (%s line %d in buffer '%s') at type %s " \
+ "index %d: got 0x%" FMT " != 0x%" FMT " %s\n", \
+ MSG, __FILE__, __LINE__, \
+ STR (EXPECTED), \
+ STR (VECT_NAME (T, W, N)), \
+ i, \
+ tmp_res.i, \
+ tmp_exp.i, \
+ strlen (COMMENT) > 0 ? COMMENT : ""); \
+ abort (); \
+ } \
+ } \
+ fprintf (stderr, "CHECKED %s\n", MSG); \
+ }
+
/* Clean buffer with a non-zero pattern to help diagnose buffer
overflows. */
#define CLEAN_PATTERN_8 0x33
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
new file mode 100644
index 0000000..a2213a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-567.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (1024)
+#define E FP16_C (663.1)
+#define F FP16_C (169.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+extern void abort ();
+
+/* Expected results for vabsh. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {A, -B, -C, D, E, F, -G, H};
+
+void
+exec_vabsh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vabsh_f16 (src[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vabsh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
new file mode 100644
index 0000000..2741f84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-567.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (1024)
+#define E FP16_C (663.1)
+#define F FP16_C (169.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+extern void abort ();
+
+/* Expected results for vaddh_f16. */
+float16_t src1[4] = {A, B, C, D};
+float16_t src2[4] = {E, F, G, H};
+float16_t expected[4] = {A + E, B + F, C + G, D + H};
+
+void
+exec_vaddh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 4; index++)
+ {
+ float16_t ret = vaddh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vaddh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
new file mode 100644
index 0000000..b9abbe9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (-56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (-63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (-4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (-57)
+#define C (1)
+#define D (25)
+#define E (-64)
+#define F (169)
+#define G (-4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtah_s32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+int32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtah_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvtah_s32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtah_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
new file mode 100644
index 0000000..e51109c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (57)
+#define C (1)
+#define D (25)
+#define E (64)
+#define F (169)
+#define G (4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtah_u32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+uint32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtah_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvtah_u32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtah_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
new file mode 100644
index 0000000..7304f57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A (123)
+#define B (-567)
+#define C (0)
+#define D (1024)
+#define E (-63)
+#define F (169)
+#define G (-4)
+#define H (77)
+#define AF FP16_C (A)
+#define BF FP16_C (B)
+#define CF FP16_C (C)
+#define DF FP16_C (D)
+#define EF FP16_C (E)
+#define FF FP16_C (F)
+#define GF FP16_C (G)
+#define HF FP16_C (H)
+
+extern void abort ();
+
+/* Expected results for vcvth_f16_s32. */
+int32_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vcvth_f16_s32 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_f16_s32 (src[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvth_f16_s32 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
new file mode 100644
index 0000000..228663d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A (123)
+#define B (567)
+#define C (0)
+#define D (1024)
+#define E (63)
+#define F (169)
+#define G (4)
+#define H (77)
+#define AF FP16_C (A)
+#define BF FP16_C (B)
+#define CF FP16_C (C)
+#define DF FP16_C (D)
+#define EF FP16_C (E)
+#define FF FP16_C (F)
+#define GF FP16_C (G)
+#define HF FP16_C (H)
+
+extern void abort ();
+
+/* Expected results for vcvth_f16_u32. */
+uint32_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vcvth_f16_u32 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_f16_u32 (src[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvth_f16_u32 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
new file mode 100644
index 0000000..395a15a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+#include <stdio.h>
+
+#define FRAC_1 1
+#define FRAC_2 2
+
+#define FP16(a) ((__fp16) (a))
+#define A (1)
+#define B (10)
+#define C (48)
+#define D (100)
+#define E (-1)
+#define F (-10)
+#define G (7)
+#define H (-7)
+
+extern void abort ();
+
+/* Expected results for vcvth_n_f16_s32. */
+int32_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {FP16 (0.5), FP16 (5), FP16 (24), FP16 (50),
+ FP16 (-0.5), FP16 (-5), FP16 (3.5), FP16 (-3.5)};
+
+float16_t expected2[8] = {FP16 (0.25), FP16 (2.5), FP16 (12), FP16 (25),
+ FP16 (-0.25), FP16 (-2.5), FP16 (1.75), FP16 (-1.75)};
+
+void
+exec_vcvth_n_f16_s32 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_n_f16_s32 (src[index], FRAC_1);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_n_f16_s32 (src[index], FRAC_2);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected2[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vcvth_n_f16_s32 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
new file mode 100644
index 0000000..41f2fda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+#include <stdio.h>
+
+#define FRAC_1 1
+#define FRAC_2 2
+
+#define FP16(a) ((__fp16) (a))
+#define A (1)
+#define B (10)
+#define C (48)
+#define D (100)
+#define E (1000)
+#define F (0)
+#define G (500)
+#define H (9)
+
+extern void abort ();
+
+/* Expected results for vcvth_n_f16_u32. */
+uint32_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {FP16 (0.5), FP16 (5), FP16 (24), FP16 (50),
+ FP16 (500), FP16 (0.0), FP16 (250), FP16 (4.5)};
+float16_t expected2[8] = {FP16 (0.25), FP16 (2.5), FP16 (12), FP16 (25),
+ FP16 (250), FP16 (0.0), FP16 (125), FP16 (2.25)};
+
+void
+exec_vcvth_n_f16_u32 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_n_f16_u32 (src[index], FRAC_1);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vcvth_n_f16_u32 (src[index], FRAC_2);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected2[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vcvth_n_f16_u32 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
new file mode 100644
index 0000000..7c22298
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+#include <stdio.h>
+
+#define FRAC_1 1
+#define FRAC_2 2
+
+#define FP16_C(a) ((__fp16) (a))
+#define A FP16_C (2.5)
+#define B FP16_C (100)
+#define C FP16_C (7.1)
+#define D FP16_C (-9.9)
+#define E FP16_C (-5.0)
+#define F FP16_C (9.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+extern void abort ();
+
+/* Expected results for vcvth_n_s32_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+int32_t expected[8] = {5, 200, 14, -19, -10, 18, -9, 154};
+int32_t expected2[8] = {10, 400, 28, -39, -20, 36, -19, 308};
+
+void
+exec_vcvth_n_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvth_n_s32_f16 (src[index], FRAC_1);
+ if (ret != expected[index])
+ abort ();
+ }
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvth_n_s32_f16 (src[index], FRAC_2);
+ if (ret != expected2[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vcvth_n_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
new file mode 100644
index 0000000..75eef3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+#include <stdio.h>
+
+#define FRAC_1 1
+#define FRAC_2 2
+
+#define FP16_C(a) ((__fp16) (a))
+#define A FP16_C (2.5)
+#define B FP16_C (100)
+#define C FP16_C (7.1)
+#define D FP16_C (9.9)
+#define E FP16_C (5.0)
+#define F FP16_C (9.1)
+#define G FP16_C (4.8)
+#define H FP16_C (77)
+
+extern void abort ();
+
+/* Expected results for vcvth_n_u32_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+uint32_t expected[8] = {5, 200, 14, 19, 10, 18, 9, 154};
+uint32_t expected2[8] = {10, 400, 28, 39, 20, 36, 19, 308};
+
+void
+exec_vcvth_n_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvth_n_u32_f16 (src[index], FRAC_1);
+ if (ret != expected[index])
+ abort ();
+ }
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvth_n_u32_f16 (src[index], FRAC_2);
+ if (ret != expected2[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vcvth_n_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
new file mode 100644
index 0000000..aba0c93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (-56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (-63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (-4.3)
+#define HF FP16_C (77.0)
+
+#define A (123)
+#define B (-56)
+#define C (0)
+#define D (24)
+#define E (-63)
+#define F (169)
+#define G (-4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvth_s32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+int32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvth_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvth_s32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvth_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
new file mode 100644
index 0000000..378103f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (4.3)
+#define HF FP16_C (77.0)
+
+#define A (123)
+#define B (56)
+#define C (0)
+#define D (24)
+#define E (63)
+#define F (169)
+#define G (4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvth_u32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+uint32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvth_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvth_u32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvth_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
new file mode 100644
index 0000000..286450c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (-56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (-63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (-4.3)
+#define HF FP16_C (77.0)
+
+#define A (123)
+#define B (-57)
+#define C (0)
+#define D (24)
+#define E (-64)
+#define F (169)
+#define G (-5)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtmh_s32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+int32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtmh_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvtmh_s32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtmh_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
new file mode 100644
index 0000000..9b75827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (56.8)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (4.3)
+#define HF FP16_C (77.0)
+
+#define A (123)
+#define B (56)
+#define C (0)
+#define D (24)
+#define E (63)
+#define F (169)
+#define G (4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtmh_u32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+uint32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtmh_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvtmh_u32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtmh_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
new file mode 100644
index 0000000..d6dc16a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (-56.5)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (-63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (-4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (-56)
+#define C (1)
+#define D (25)
+#define E (-64)
+#define F (169)
+#define G (-4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtnh_s32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+int32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtnh_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvtnh_s32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtnh_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
new file mode 100644
index 0000000..a2d5089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (56.5)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (56)
+#define C (1)
+#define D (25)
+#define E (64)
+#define F (169)
+#define G (4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtnh_u32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+uint32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtnh_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvtnh_u32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtnh_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
new file mode 100644
index 0000000..be7af56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (-56.5)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (-63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (-4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (-56)
+#define C (1)
+#define D (25)
+#define E (-63)
+#define F (170)
+#define G (-4)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtph_s32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+int32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtph_s32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ int32_t ret = vcvtph_s32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtph_s32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
new file mode 100644
index 0000000..ec6dba1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define AF FP16_C (123.9)
+#define BF FP16_C (56.5)
+#define CF FP16_C (0.7)
+#define DF FP16_C (24.6)
+#define EF FP16_C (63.5)
+#define FF FP16_C (169.4)
+#define GF FP16_C (4.3)
+#define HF FP16_C (77.0)
+
+#define A (124)
+#define B (57)
+#define C (1)
+#define D (25)
+#define E (64)
+#define F (170)
+#define G (5)
+#define H (77)
+
+extern void abort ();
+
+/* Expected results for vcvtph_u32_f16. */
+float16_t src[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+uint32_t expected[8] = {A, B, C, D, E, F, G, H};
+
+void
+exec_vcvtph_u32_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ uint32_t ret = vcvtph_u32_f16 (src[index]);
+ if (ret != expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vcvtph_u32_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
new file mode 100644
index 0000000..6fd7f5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (13.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (12)
+#define E FP16_C (63.1)
+#define F FP16_C (19.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+#define I FP16_C (0.7)
+#define J FP16_C (-78)
+#define K FP16_C (11.23)
+#define L FP16_C (98)
+#define M FP16_C (87.1)
+#define N FP16_C (-8)
+#define O FP16_C (-1.1)
+#define P FP16_C (-9.7)
+
+extern void abort ();
+
+/* Expected results for vdivh. */
+float16_t src1[8] = {A, B, C, D, I, J, K, L};
+float16_t src2[8] = {E, F, G, H, M, N, O, P};
+float16_t expected[8] = {A / E, B / F, C / G, D / H,
+ I / M, J / N, K / O, L / P};
+
+void
+exec_vdivh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vdivh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vdivh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
new file mode 100644
index 0000000..ba8f9c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A0 FP16_C (123.4)
+#define B0 FP16_C (-5.8)
+#define C0 FP16_C (-3.8)
+#define D0 FP16_C (10)
+
+#define A1 FP16_C (12.4)
+#define B1 FP16_C (-5.8)
+#define C1 FP16_C (90.8)
+#define D1 FP16_C (24)
+
+#define A2 FP16_C (23.4)
+#define B2 FP16_C (-5.8)
+#define C2 FP16_C (8.9)
+#define D2 FP16_C (4)
+
+#define E0 FP16_C (3.4)
+#define F0 FP16_C (-55.8)
+#define G0 FP16_C (-31.8)
+#define H0 FP16_C (2)
+
+#define E1 FP16_C (123.4)
+#define F1 FP16_C (-5.8)
+#define G1 FP16_C (-3.8)
+#define H1 FP16_C (102)
+
+#define E2 FP16_C (4.9)
+#define F2 FP16_C (-15.8)
+#define G2 FP16_C (39.8)
+#define H2 FP16_C (49)
+
+extern void abort ();
+
+/* Expected results for vfmah_f16. */
+
+float16_t src1[8] = {A0, B0, C0, D0, E0, F0, G0, H0};
+float16_t src2[8] = {A1, B1, C1, D1, E1, F1, G1, H1};
+float16_t src3[8] = {A2, B2, C2, D2, E2, F2, G2, H2};
+float16_t expected[8] = {A0 + A1 * A2, B0 + B1 * B2,
+ C0 + C1 * C2, D0 + D1 * D2,
+ E0 + E1 * E2, F0 + F1 * F2,
+ G0 + G1 * G2, H0 + H1 * H2};
+
+void
+exec_vfmah_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vfmah_f16 (src1[index], src2[index], src3[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vfmah_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
new file mode 100644
index 0000000..c132295
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A0 FP16_C (123.4)
+#define B0 FP16_C (-5.8)
+#define C0 FP16_C (-3.8)
+#define D0 FP16_C (10)
+
+#define A1 FP16_C (12.4)
+#define B1 FP16_C (-5.8)
+#define C1 FP16_C (90.8)
+#define D1 FP16_C (24)
+
+#define A2 FP16_C (23.4)
+#define B2 FP16_C (-5.8)
+#define C2 FP16_C (8.9)
+#define D2 FP16_C (4)
+
+#define E0 FP16_C (3.4)
+#define F0 FP16_C (-55.8)
+#define G0 FP16_C (-31.8)
+#define H0 FP16_C (2)
+
+#define E1 FP16_C (123.4)
+#define F1 FP16_C (-5.8)
+#define G1 FP16_C (-3.8)
+#define H1 FP16_C (102)
+
+#define E2 FP16_C (4.9)
+#define F2 FP16_C (-15.8)
+#define G2 FP16_C (39.8)
+#define H2 FP16_C (49)
+
+extern void abort ();
+
+/* Expected results for vfmsh_f16. */
+
+float16_t src1[8] = {A0, B0, C0, D0, E0, F0, G0, H0};
+float16_t src2[8] = {A1, B1, C1, D1, E1, F1, G1, H1};
+float16_t src3[8] = {A2, B2, C2, D2, E2, F2, G2, H2};
+float16_t expected[8] = {A0 + -A1 * A2, B0 + -B1 * B2,
+ C0 + -C1 * C2, D0 + -D1 * D2,
+ E0 + -E1 * E2, F0 + -F1 * F2,
+ G0 + -G1 * G2, H0 + -H1 * H2};
+
+void
+exec_vfmsh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vfmsh_f16 (src1[index], src2[index], src3[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+
+}
+
+int
+main (void)
+{
+ exec_vfmsh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
new file mode 100644
index 0000000..7474cda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-567.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (1024)
+#define E FP16_C (663.1)
+#define F FP16_C (169.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+#define I FP16_C (0.7)
+#define J FP16_C (-78)
+#define K FP16_C (101.23)
+#define L FP16_C (98)
+#define M FP16_C (870.1)
+#define N FP16_C (-8781)
+#define O FP16_C (__builtin_inff ()) /* +Inf */
+#define P FP16_C (-__builtin_inff ()) /* -Inf */
+
+extern void abort ();
+
+/* Expected results for vmaxnmh. */
+float16_t src1[8] = {A, B, C, D, I, J, K, L};
+float16_t src2[8] = {E, F, G, H, M, N, O, P};
+float16_t expected[8] = {E, F, G, D, M, J, O, L};
+
+void
+exec_vmaxnmh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vmaxnmh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vmaxnmh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
new file mode 100644
index 0000000..7e01549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-567.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (1024)
+#define E FP16_C (663.1)
+#define F FP16_C (169.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+#define I FP16_C (0.7)
+#define J FP16_C (-78)
+#define K FP16_C (101.23)
+#define L FP16_C (98)
+#define M FP16_C (870.1)
+#define N FP16_C (-8781)
+#define O FP16_C (__builtin_inff ()) /* +Inf */
+#define P FP16_C (-__builtin_inff ()) /* -Inf */
+
+extern void abort ();
+
+/* Expected results for vminnmh. */
+float16_t src1[8] = {A, B, C, D, I, J, K, L};
+float16_t src2[8] = {E, F, G, H, M, N, O, P};
+float16_t expected[8] = {A, B, C, H, I, N, K, P};
+
+void
+exec_vminnmh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vminnmh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vminnmh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
new file mode 100644
index 0000000..80244a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (13.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (12)
+#define E FP16_C (63.1)
+#define F FP16_C (19.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+#define I FP16_C (0.7)
+#define J FP16_C (-78)
+#define K FP16_C (11.23)
+#define L FP16_C (98)
+#define M FP16_C (87.1)
+#define N FP16_C (-8)
+#define O FP16_C (-1.1)
+#define P FP16_C (-9.7)
+
+extern void abort ();
+
+/* Expected results for vmulh. */
+float16_t src1[8] = {A, B, C, D, I, J, K, L};
+float16_t src2[8] = {E, F, G, H, M, N, O, P};
+float16_t expected[8] = {A * E, B * F, C * G, D * H,
+ I * M, J * N, K * O, L * P};
+void
+exec_vmulh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vmulh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vmulh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
new file mode 100644
index 0000000..6fd6c11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define FP16_C(a) ((__fp16) a)
+
+#define AS 123.9
+#define BS -56.8
+#define CS 0.7
+#define DS 24.6
+#define ES -63.5
+#define FS 169.4
+#define GS -4.3
+#define HS 77.0
+
+#define A FP16_C (AS)
+#define B FP16_C (BS)
+#define C FP16_C (CS)
+#define D FP16_C (DS)
+#define E FP16_C (ES)
+#define F FP16_C (FS)
+#define G FP16_C (GS)
+#define H FP16_C (HS)
+
+#define AF FP16_C (-AS)
+#define BF FP16_C (-BS)
+#define CF FP16_C (-CS)
+#define DF FP16_C (-DS)
+#define EF FP16_C (-ES)
+#define FF FP16_C (-FS)
+#define GF FP16_C (-GS)
+#define HF FP16_C (-HS)
+
+
+
+extern void abort ();
+
+/* Expected results for vnegh_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vnegh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vnegh_f16 (src[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vnegh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
new file mode 100644
index 0000000..e8dc8c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-663.1)
+#define F FP16_C (-144.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-57.0)
+#define CF FP16_C (35.0)
+#define DF FP16_C (25.0)
+#define EF FP16_C (-663.0)
+#define FF FP16_C (-145.0)
+#define GF FP16_C (5.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndah_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndah_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndah_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndah_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
new file mode 100644
index 0000000..c2c3db3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (1024.5)
+#define E FP16_C (-663.1)
+#define F FP16_C (-144.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-56.0)
+#define CF FP16_C (34.0)
+#define DF FP16_C (1024.0)
+#define EF FP16_C (-663.0)
+#define FF FP16_C (-144.0)
+#define GF FP16_C (4.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndh_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndh_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
new file mode 100644
index 0000000..0250965
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-663.1)
+#define F FP16_C (-144.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-57.0)
+#define CF FP16_C (35.0)
+#define DF FP16_C (24.0)
+#define EF FP16_C (-663.0)
+#define FF FP16_C (-144.0)
+#define GF FP16_C (5.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndih_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndih_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndih_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndih_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
new file mode 100644
index 0000000..c098281
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-63.1)
+#define F FP16_C (-144.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-57.0)
+#define CF FP16_C (34.0)
+#define DF FP16_C (24.0)
+#define EF FP16_C (-64.0)
+#define FF FP16_C (-145.0)
+#define GF FP16_C (4.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndmh_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndmh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndmh_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndmh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
new file mode 100644
index 0000000..227d9cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-63.1)
+#define F FP16_C (-143.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-57.0)
+#define CF FP16_C (35.0)
+#define DF FP16_C (24.0)
+#define EF FP16_C (-63.0)
+#define FF FP16_C (-144.0)
+#define GF FP16_C (5.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndnh_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndnh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndnh_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndnh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
new file mode 100644
index 0000000..14af2ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-63.1)
+#define F FP16_C (-143.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (124.0)
+#define BF FP16_C (-56.0)
+#define CF FP16_C (35.0)
+#define DF FP16_C (25.0)
+#define EF FP16_C (-63.0)
+#define FF FP16_C (-143.0)
+#define GF FP16_C (5.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndph_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndph_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndph_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndph_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
new file mode 100644
index 0000000..90f6bd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-56.8)
+#define C FP16_C (34.8)
+#define D FP16_C (24.5)
+#define E FP16_C (-663.1)
+#define F FP16_C (-144.5)
+#define G FP16_C (4.8)
+#define H FP16_C (77.0)
+
+#define AF FP16_C (123.0)
+#define BF FP16_C (-57.0)
+#define CF FP16_C (35.0)
+#define DF FP16_C (24.0)
+#define EF FP16_C (-663.0)
+#define FF FP16_C (-144.0)
+#define GF FP16_C (5.0)
+#define HF FP16_C (77.0)
+
+
+extern void abort ();
+
+/* Expected results for vrndxh_f16. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {AF, BF, CF, DF, EF, FF, GF, HF};
+
+void
+exec_vrndxh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vrndxh_f16 (src[index]);
+ if (* (short *) &ret != * (short *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vrndxh_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
new file mode 100644
index 0000000..e482318
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+extern void abort (void);
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (12.4)
+#define B FP16_C (5.8)
+#define C FP16_C (3.8)
+#define D FP16_C (10)
+#define E FP16_C (66.1)
+#define F FP16_C (16.1)
+#define G FP16_C (4.8)
+#define H FP16_C (77)
+
+#define SQRT_A FP16_C (3.5213)
+#define SQRT_B FP16_C (2.4083)
+#define SQRT_C FP16_C (1.9493)
+#define SQRT_D FP16_C (3.1622)
+#define SQRT_E FP16_C (8.1301)
+#define SQRT_F FP16_C (4.0124)
+#define SQRT_G FP16_C (2.1908)
+#define SQRT_H FP16_C (8.7749)
+
+
+/* Expected results for vsqrth. */
+float16_t src[8] = {A, B, C, D, E, F, G, H};
+float16_t expected[8] = {SQRT_A, SQRT_B, SQRT_C, SQRT_D,
+ SQRT_E, SQRT_F, SQRT_G, SQRT_H};
+
+/* The acceptable difference between the bit-patterns for the expected and
+ actual results. */
+const int bias = 0;
+
+void
+exec_vsqrth_f16 (void)
+{
+ int index;
+ for (index = 0; index < 8; index++)
+ {
+ float16_t ret = vsqrth_f16 (src[index]);
+ uint32_t diff;
+
+ diff = (* (uint16_t *) &ret) - (* (uint16_t *) &expected[index]);
+ if (diff > bias)
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vsqrth_f16 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
new file mode 100644
index 0000000..455f363
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+#define FP16_C(a) ((__fp16) a)
+#define A FP16_C (123.4)
+#define B FP16_C (-567.8)
+#define C FP16_C (-34.8)
+#define D FP16_C (1024)
+#define E FP16_C (663.1)
+#define F FP16_C (169.1)
+#define G FP16_C (-4.8)
+#define H FP16_C (77)
+
+extern void abort ();
+
+/* Expected results for vsubh. */
+float16_t src1[4] = {A, B, C, D};
+float16_t src2[4] = {E, F, G, H};
+float16_t expected[4] = {A - E, B - F, C - G, D - H};
+
+void
+exec_vsubh_f16 (void)
+{
+ int index;
+
+ for (index = 0; index < 4; index++)
+ {
+ float16_t ret = vsubh_f16 (src1[index], src2[index]);
+ if (* (uint16_t *) &ret != * (uint16_t *) &expected[index])
+ abort ();
+ }
+}
+
+int
+main (void)
+{
+ exec_vsubh_f16 ();
+ return 0;
+}
--
2.1.4
