[PATCH, PR target/71114] Fix constants conversion in STV pass

[Ilya Enkovich]

Hi,

This patch fixes an insertion point for instructions generated by
validize_mem in dimode_scalar_chain::convert_op.  Patch also fixes
scanned instruction pattern to fix test for Darwin.

I bootstrapped and regtested it on x86_64-pc-linus gnu.
Dominique d'Humieres tested it for Darwin.  OK for trunk?

Thanks,
Ilya
--
gcc/

2016-05-17  Ilya Enkovich  <ilya.enkov...@intel.com>

        PR target/71114
        * config/i386/i386.c (dimode_scalar_chain::convert_op): Fix
        insertion point for instructions generated by validize_mem.

gcc/testsuite/

2016-05-17  Dominique d'Humieres  <domi...@lps.ens.fr>
            Ilya Enkovich  <ilya.enkov...@intel.com>

        PR target/71114
        * gcc.target/i386/pr70799-1.c: Fix scan for Darwin.


diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 046717b..47d2e7d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3688,7 +3688,13 @@ dimode_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
                                        gen_rtvec (2, *op, const0_rtx));
 
       if (!standard_sse_constant_p (vec_cst, V2DImode))
-       vec_cst = validize_mem (force_const_mem (V2DImode, vec_cst));
+       {
+         start_sequence ();
+         vec_cst = validize_mem (force_const_mem (V2DImode, vec_cst));
+         rtx_insn *seq = get_insns ();
+         end_sequence ();
+         emit_insn_before (seq, insn);
+       }
 
       emit_insn_before (gen_move_insn (tmp, vec_cst), insn);
       *op = tmp;
diff --git a/gcc/testsuite/gcc.target/i386/pr70799-1.c 
b/gcc/testsuite/gcc.target/i386/pr70799-1.c
index 0abbfb9..f4e42fa 100644
--- a/gcc/testsuite/gcc.target/i386/pr70799-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr70799-1.c
@@ -3,7 +3,7 @@
 /* { dg-options "-O2 -march=slm" } */
 /* { dg-final { scan-assembler "pxor" } } */
 /* { dg-final { scan-assembler "pcmpeqd" } } */
-/* { dg-final { scan-assembler "movdqa\[ \\t\]+.LC0" } } */
+/* { dg-final { scan-assembler "movdqa\[ \\t\]+.?LC0" } } */
 
 long long a, b, c;