On 04 May 21:35, Jakub Jelinek wrote: > Hi! > > Not sure how to easily construct a testcase for this (these insns are > usually used for vectorization, and then it really depends on register > pressure). > But in any case, looking at documentation it seems all the used insns are > available (generally even for further patches, what I'm looking for is > whether the insns are available already in AVX512F, or, if all the operands > are 128-bit or 256-bit vectors, in AVX512VL, or if they need further ISA > extensions; HARD_REGNO_MODE_OK should guarantee that the 128-bit and 256-bit > vectors would not be assigned to xmm16+ unless -mavx512vl). > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? OK for trunk.
-- Thanks, K > > 2016-05-04 Jakub Jelinek <ja...@redhat.com> > > * config/i386/sse.md (*avx_cvtpd2dq256_2, *avx_cvtps2pd256_2): Use > v constraint instead of x. > > --- gcc/config/i386/sse.md.jj 2016-05-04 14:36:08.000000000 +0200 > +++ gcc/config/i386/sse.md 2016-05-04 15:16:44.180894303 +0200 > @@ -4735,9 +4735,9 @@ (define_expand "avx_cvtpd2dq256_2" > "operands[2] = CONST0_RTX (V4SImode);") > > (define_insn "*avx_cvtpd2dq256_2" > - [(set (match_operand:V8SI 0 "register_operand" "=x") > + [(set (match_operand:V8SI 0 "register_operand" "=v") > (vec_concat:V8SI > - (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")] > + (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")] > UNSPEC_FIX_NOTRUNC) > (match_operand:V4SI 2 "const0_operand")))] > "TARGET_AVX" > @@ -5050,10 +5050,10 @@ (define_insn "<sse2_avx_avx512f>_cvtps2p > (set_attr "mode" "<MODE>")]) > > (define_insn "*avx_cvtps2pd256_2" > - [(set (match_operand:V4DF 0 "register_operand" "=x") > + [(set (match_operand:V4DF 0 "register_operand" "=v") > (float_extend:V4DF > (vec_select:V4SF > - (match_operand:V8SF 1 "nonimmediate_operand" "xm") > + (match_operand:V8SF 1 "nonimmediate_operand" "vm") > (parallel [(const_int 0) (const_int 1) > (const_int 2) (const_int 3)]))))] > "TARGET_AVX" > > Jakub
