On 25/04/16 02:43, Sandra Loosemore wrote:
On 04/22/2016 03:57 AM, James Greenhalgh wrote:
On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote:
Hi all,
Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
If there's anything I've missed it's purely my oversight, feel free to add
entries or suggest improvements.
For me, I'm mostly happy with the wording below (I've tried to be
helpful inline). But I'm not as conscientious at checking grammar as others
in the community. So this is OK from an AArch64 target perspective with
the changes below, but wait a short while to give Gerald or Sandra a chance
to comment.
I haven't done a careful review of the whole section of existing text, but I
did notice a few things in text not being touched by this patch:
+ <li>
The new command line options <code>-march=native</code>,
s/command line options/command-line options/
<code>-mcpu=native</code> and <code>-mtune=native</code> are now
available on native AArch64 GNU/Linux systems. Specifying
these options will cause GCC to auto-detect the host CPU and
s/will cause/causes/
rewrite these options to the optimal setting for that system.
s/rewrite these options to the optimal/choose the/
- <code>-fpic</code> is now supported by the AArch64 target when
generating
+ <code>-fpic</code> is now supported when generating
code for the small code model (<code>-mcmodel=small</code>). The size
of
the global offset table (GOT) is limited to 28KiB under the LP64 SysV
ABI
, and 15KiB under the ILP32 SysV ABI.
Move the comma directly after "ABI", not separated by newline and whitespace.
Thanks, I've incorporated your and James' feedback.
Since James ok'd the content of the patch from an AArch64 perspective
I'll commit this later today if I receive no further feedback.
Thanks,
Kyrill
-Sandra
Index: htdocs/gcc-6/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.73
diff -U 3 -r1.73 changes.html
--- htdocs/gcc-6/changes.html 7 Apr 2016 09:38:31 -0000 1.73
+++ htdocs/gcc-6/changes.html 25 Apr 2016 09:10:25 -0000
@@ -328,29 +328,90 @@
<h3 id="aarch64">AArch64</h3>
<ul>
<li>
- The new command line options <code>-march=native</code>,
+ A number of AArch64-specific options have been added. The most
+ important ones are summarised in this section but for usage
+ instructions please refer to the documentation.
+ </li>
+ <li>
+ The new command-line options <code>-march=native</code>,
<code>-mcpu=native</code> and <code>-mtune=native</code> are now
available on native AArch64 GNU/Linux systems. Specifying
- these options will cause GCC to auto-detect the host CPU and
- rewrite these options to the optimal setting for that system.
- If GCC is unable to detect the host CPU these options have no effect.
+ these options causes GCC to auto-detect the host CPU and
+ choose the optimal setting for that system.
</li>
<li>
- <code>-fpic</code> is now supported by the AArch64 target when generating
+ <code>-fpic</code> is now supported when generating
code for the small code model (<code>-mcmodel=small</code>). The size of
- the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI
- , and 15KiB under the ILP32 SysV ABI.
+ the global offset table (GOT) is limited to 28KiB under the LP64
+ SysV ABI, and 15KiB under the ILP32 SysV ABI.
</li>
<li>
- The AArch64 port now supports target attributes and pragmas. Please
- refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes";>
- documentation</a> for details of available attributes and
+ Target attributes and pragmas are now supported. Please
+ refer to the documentation for details of available attributes and
pragmas as well as usage instructions.
</li>
<li>
Link-time optimization across translation units with different
target-specific options is now supported.
</li>
+ <li>
+ The option <code>-mtls-size=</code> is now supported. It can be used to
+ specify the bit size of TLS offsets, allowing GCC to generate
+ better TLS instruction sequences.
+ </li>
+ <li>
+ The option <code>-fno-plt</code> is now fully functional.
+ </li>
+ <li>
+ The ARMv8.1-A architecture and the Large System Extensions are now
+ supported. They can be used by specifying the
+ <code>-march=armv8.1-a</code> option. Additionally, the
+ <code>+lse</code> option extension can be used in a similar fashion
+ to other option extensions.
+ The Large System Extensions introduce new instructions that are used
+ in the implementation of atomic operations.
+ </li>
+ <li>
+ The ACLE half-precision floating-point type <code>__fp16</code> is now
+ supported in the C and C++ languages.
+ </li>
+ <li>
+ The ARM Cortex-A35 processor is now supported via the
+ <code>-mcpu=cortex-a35</code> and <code>-mtune=cortex-a35</code>
+ options as well as the equivalent target attributes and pragmas.
+ </li>
+ <li>
+ Code generation for the ARM Cortex-A57 processor is improved.
+ Among general code generation improvements, a better algorithm is
+ added for allocating registers to floating-point multiply-accumulate
+ instructions offering increased performance when compiling with
+ <code>-mcpu=cortex-a57</code> or <code>-mtune=cortex-a57</code>.
+ </li>
+ <li>Code generation for the ARM Cortex-A53 processor is improved.
+ A more accurate instruction scheduling model for the processor is
+ now used, and a number of compiler tuning parameters have been set
+ to offer increased performance when compiling with
+ <code>-mcpu=cortex-a53</code> or <code>-mtune=cortex-a53</code>.
+ </li>
+ <li>Code generation for the Samsung Exynos M1 processor is improved.
+ A more accurate instruction scheduling model for the processor is
+ now used, and a number of compiler tuning parameters have been set
+ to offer increased performance when compiling with
+ <code>-mcpu=exynos-m1</code> or <code>-mtune=exynos-m1</code>.
+ </li>
+ <li>
+ Improvements in the generation of conditional branches and literal
+ pools were made to allow the compiler to compile functions of a large
+ size. Constant pools are now placed into separate rodata sections.
+ The new option <code>-mpc-relative-literal-loads</code> is
+ introduced to generate per-function literal pools, limiting the maximum
+ size of functions to 1MiB.
+ </li>
+ <li>
+ Several correctness issues with generation of Advanced SIMD instructions
+ for big-endian targets have been fixed resulting in improved code
+ generation for ACLE intrinsics with <code>-mbig-endian</code>.
+ </li>
</ul>
<h3 id="arm">ARM</h3>
