On Tue, Apr 19, 2016 at 8:08 AM, Uros Bizjak <ubiz...@gmail.com> wrote: > On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu <hongjiu...@intel.com> wrote: >> >> From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software >> developer manual volume 2, only legacy SSE instructions with memory >> operand not 16-byte aligned get General Protection fault. There is >> no need to check 1, 2, 4, 8 byte alignments. Since x86 backend has >> accurate constraints and predicates for 16-byte alignment, we can >> remove ix86_legitimate_combined_insn. >> >> Tested on x86-64. OK for trunk? > > No. This function also handles cases where invalid hard register gets > propagated into the insn during the combine pass, leading to spill > failure later. >
ix86_legitimate_combined_insn was added to work around the reload issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46829 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46843 LRA doesn't have those limitation. Removing ix86_legitimate_combined_insn causes no regressions. -- H.J.
