The NPS400 is an ARC700 variant from Mellanox (formally EZChip). This patch series adds a new GCC build target with the mellanox vendor string, that configures the ARC backend to support NPS400.
This patch series is intended for GCC 7, Stage 1, once it reopens. I am posting early in the hope that I could get an early review, especially on patch #1, the build infrastructure, then if I need to rework anything I can get started on it sooner. I've run regression tests against a standard arc-elf target, and the results look good. All feedback appreciated. Thanks, Andrew --- Andrew Burgess (10): gcc: Add support for mellanox nps400 arc variant gcc/arc: Add -munaligned-access option for nps400 gcc/arc: generate jump tables in code section for nps400 gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns gcc/arc: convert some constraints to define_constraint gcc/arc: Add support for nps400 cmem xld/xst instructions gcc/arc: Add nps400 bitops support gcc/arc: Mask integer 'L' operands to 32-bit gcc/arc: Add an nps400 specific testcase gcc/arc: Add __NPS400__ define for nps400 targets gcc/ChangeLog.NPS400 | 122 +++++++ gcc/config.gcc | 10 + gcc/config/arc/arc.c | 67 +++- gcc/config/arc/arc.h | 35 +- gcc/config/arc/arc.md | 567 +++++++++++++++++++++++------- gcc/config/arc/arc.opt | 14 +- gcc/config/arc/constraints.md | 86 ++++- gcc/config/arc/predicates.md | 19 + gcc/config/arc/t-nps400 | 21 ++ gcc/testsuite/ChangeLog.NPS400 | 44 +++ gcc/testsuite/gcc.target/arc/cmem-1.c | 10 + gcc/testsuite/gcc.target/arc/cmem-2.c | 10 + gcc/testsuite/gcc.target/arc/cmem-3.c | 10 + gcc/testsuite/gcc.target/arc/cmem-4.c | 10 + gcc/testsuite/gcc.target/arc/cmem-5.c | 10 + gcc/testsuite/gcc.target/arc/cmem-6.c | 10 + gcc/testsuite/gcc.target/arc/cmem-7.c | 26 ++ gcc/testsuite/gcc.target/arc/cmem-ld.inc | 16 + gcc/testsuite/gcc.target/arc/cmem-st.inc | 18 + gcc/testsuite/gcc.target/arc/extzv-1.c | 11 + gcc/testsuite/gcc.target/arc/insv-1.c | 21 ++ gcc/testsuite/gcc.target/arc/insv-2.c | 18 + gcc/testsuite/gcc.target/arc/movb-1.c | 13 + gcc/testsuite/gcc.target/arc/movb-2.c | 13 + gcc/testsuite/gcc.target/arc/movb-3.c | 13 + gcc/testsuite/gcc.target/arc/movb-4.c | 13 + gcc/testsuite/gcc.target/arc/movb-5.c | 13 + gcc/testsuite/gcc.target/arc/movb_cl-1.c | 9 + gcc/testsuite/gcc.target/arc/movb_cl-2.c | 11 + gcc/testsuite/gcc.target/arc/movbi_cl-1.c | 9 + gcc/testsuite/gcc.target/arc/movh_cl-1.c | 27 ++ gcc/testsuite/gcc.target/arc/movl-1.c | 17 + gcc/testsuite/gcc.target/arc/mrgb-1.c | 14 + gcc/testsuite/gcc.target/arc/nps400-1.c | 23 ++ gcc/testsuite/gcc.target/arc/setmem-1.c | 13 + gcc/testsuite/gcc.target/arc/setmem-2.c | 18 + gcc/testsuite/gcc.target/arc/setmem-3.c | 13 + gcc/testsuite/gcc.target/arc/setmem-4.c | 18 + 38 files changed, 1231 insertions(+), 161 deletions(-) create mode 100644 gcc/config/arc/t-nps400 create mode 100644 gcc/testsuite/ChangeLog.NPS400 create mode 100644 gcc/testsuite/gcc.target/arc/cmem-1.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-2.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-3.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-4.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-5.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-6.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-7.c create mode 100644 gcc/testsuite/gcc.target/arc/cmem-ld.inc create mode 100644 gcc/testsuite/gcc.target/arc/cmem-st.inc create mode 100644 gcc/testsuite/gcc.target/arc/extzv-1.c create mode 100644 gcc/testsuite/gcc.target/arc/insv-1.c create mode 100644 gcc/testsuite/gcc.target/arc/insv-2.c create mode 100644 gcc/testsuite/gcc.target/arc/movb-1.c create mode 100644 gcc/testsuite/gcc.target/arc/movb-2.c create mode 100644 gcc/testsuite/gcc.target/arc/movb-3.c create mode 100644 gcc/testsuite/gcc.target/arc/movb-4.c create mode 100644 gcc/testsuite/gcc.target/arc/movb-5.c create mode 100644 gcc/testsuite/gcc.target/arc/movb_cl-1.c create mode 100644 gcc/testsuite/gcc.target/arc/movb_cl-2.c create mode 100644 gcc/testsuite/gcc.target/arc/movbi_cl-1.c create mode 100644 gcc/testsuite/gcc.target/arc/movh_cl-1.c create mode 100644 gcc/testsuite/gcc.target/arc/movl-1.c create mode 100644 gcc/testsuite/gcc.target/arc/mrgb-1.c create mode 100644 gcc/testsuite/gcc.target/arc/nps400-1.c create mode 100644 gcc/testsuite/gcc.target/arc/setmem-1.c create mode 100644 gcc/testsuite/gcc.target/arc/setmem-2.c create mode 100644 gcc/testsuite/gcc.target/arc/setmem-3.c create mode 100644 gcc/testsuite/gcc.target/arc/setmem-4.c -- 2.6.4
