On 18.02.2016 12:36, Tom de Vries wrote: > On 15/02/16 12:29, Bernd Edlinger wrote: >> Here is a patch that puts each value on it's own 8-byte aligned memory >> location. From my experience with tsan tests, sharing shadow memory >> slots between v and q or o is the most likely explanation for the >> occasional >> inability to spot the race condition on v, thus the test case fails, >> because >> the return code is 0, and the expected output is not found. >> >> Boot-strapped/regression tested on x86_64-linux-gnu. >> >> OK for trunk? >> > > Hi, > > Could you add 'PR testsuite/68580' to the log entry when committing? >
Yes, of course, thanks. Could someone take the time and review this patch? I don't think it can cause any trouble for gcc-6 and/or gcc-5 even at stage 4. Is it OK for trunk and gcc-5-branch? Thanks Bernd. > Thanks, > - Tom > >> patch-pr68580.diff >> >> >> 2016-02-15 Bernd Edlinger<bernd.edlin...@hotmail.de> >> >> * c-c++-common/tsan/pr65400-1.c (v, q, o): Make 8-byte aligned. >> >> --- gcc/testsuite/c-c++-common/tsan/pr65400-1.c.jj 2015-03-19 >> 08:53:38.000000000 +0100 >> +++ gcc/testsuite/c-c++-common/tsan/pr65400-1.c 2016-02-15 >> 11:09:18.852320827 +0100 >> @@ -7,9 +7,9 @@ >> #include "tsan_barrier.h" >> >> static pthread_barrier_t barrier; >> -int v; >> -int q; >> -int o; >> +int v __attribute__((aligned(8))); >> +int q __attribute__((aligned(8))); >> +int o __attribute__((aligned(8))); >> extern void baz4 (int *); >> >> __attribute__((noinline, noclone)) int >
