Re: [ARM][PR69194] Fix ICE in in extract_insn

[Kugan]

On 09/01/16 07:01, Jakub Jelinek wrote:
> On Fri, Jan 08, 2016 at 11:43:34AM -0800, Jim Wilson wrote:
>> Here is a smaller simpler testcase.  Only the first four args get
>> passed in regs, so the fifth one has address equal to the virtual
>> incoming args reg which triggers the failure.
>>
>> typedef __simd128_float32_t float32x4_t;
>> float32x4_t
>> sub (float32x4_t a, float32x4_t b, float32x4_t c, float32x4_t d, float32x4_t 
>> e)
>> {
>>   return __builtin_neon_vld1v4sf((const float *)&e);
>> }
>>
>> The original testcase failed with linaro gcc 4.9.  I verified that
>> this testcase fails with FSF gcc-5.3.0.
> 
> Looks much better.  I'll defer to ARM maintainers to ack this.

Thanks for the review. Please find the patch with the required changes.
Regression tested with trunk and gcc-5 for arn-none-linux-gnu with no
new regression. Is this OK ?

Kugan


2016-01-10  Kugan Vivekanandarajah  <kug...@linaro.org>
            Jim Wilson  <jim.wil...@linaro.org>

        PR target/69194
        * config/arm/arm-builtins.c (arm_expand_neon_args): Call
        copy_to_mode_reg instead of force_reg.

gcc/testsuite/ChangeLog:

2016-01-10  Kugan Vivekanandarajah  <kug...@linaro.org>
            Jim Wilson  <jim.wil...@linaro.org>

        PR target/69194
        * gcc.target/arm/pr69194.C: New test.


diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 11cd17d..fbdf0a3 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -2146,7 +2146,8 @@ constant_arg:
              if (!(*insn_data[icode].operand[opno].predicate)
                    (op[argc], mode[argc]))
                op[argc] = (replace_equiv_address
-                           (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
+                           (op[argc],
+                            copy_to_mode_reg (Pmode, XEXP (op[argc], 0))));
               break;
 
            case NEON_ARG_STOP:
diff --git a/gcc/testsuite/gcc.target/arm/pr69194.c 
b/gcc/testsuite/gcc.target/arm/pr69194.c
index e69de29..10630c1 100644
--- a/gcc/testsuite/gcc.target/arm/pr69194.c
+++ b/gcc/testsuite/gcc.target/arm/pr69194.c
@@ -0,0 +1,12 @@
+/* PR target/69194 */
+/* { dg-do-compile } */
+/* { dg-require-effective-target arm_neon } */
+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=hard" } */
+
+typedef __simd128_float32_t float32x4_t;
+
+float32x4_t
+sub (float32x4_t a, float32x4_t b, float32x4_t c, float32x4_t d, float32x4_t e)
+{
+  return __builtin_neon_vld1v4sf((const float *)&e);
+}