Hi, Wilco.
On 12/15/2015 04:32 AM, Wilco Dijkstra wrote:
-----Original Message-----
From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
Sent: 17 November 2015 18:36
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
(v2 version removes 4 enums)
This patch adds support for FCCMP. This is trivial with the new CCMP
representation - remove the restriction of FP in ccmp.c and add
FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.
OK for commit?
ChangeLog:
2015-11-18 Wilco Dijkstra <wdijk...@arm.com>
* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
(fccmpe<mode>): Likewise.
(fcmp): Rename to fcmp and globalize pattern.
(fcmpe): Likewise.
* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP support.
(aarch64_gen_ccmp_next): Add FP support.
gcc/testsuite/
* gcc.target/aarch64/ccmp_1.c: New testcase.
Add support for the FCCMP insn types
2016-01-04 Evandro Menezes <e.mene...@samsung.com>
gcc/
* config/aarch64/aarch64.md (fccmp): Change insn type.
(fccmpe): Likewise.
* config/aarch64/thunderx.md (thunderx_fcmp): Add
"fccmp{s,d}" types.
* config/arm/types.md (fccmps): Add new insn type.
(fccmpd): Likewise.
* config/arm/arm1020e.md (v10_ffarith): Add "fccmp{s,d}" types.
* config/arm/cortex-a17-neon.md (cortex_a17_vfp_cmp): Likewise.
* config/arm/cortex-a5.md (cortex_a5_fpalu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
* config/arm/cortex-a7.md (cortex_a7_fpalu): Likewise.
* config/arm/cortex-a8-neon.md (cortex_a8_vfp_farith):
Likewise.
* config/arm/cortex-a9.md (cortex_a9_fcmp): Likewise.
* config/arm/cortex-m7.md (cortex_m7_fpalu): Likewise.
* config/arm/marvell-pj4.md (pj4_vfp_cpy): Likewise.
* config/arm/vfp11.md (vfp_ffarith): Likewise.
* config/arm/xgene1.md (xgene1_fcmp): Likewise.
* config/arm/cortex-a15-neon.md (cortex_a15_vfp_cmps): Add
"fccmps"
type.
(cortex_a15_vfp_cmpd): Add "fccmpd" type.
* config/arm/cortex-m4-fpu.md (cortex_m4_fcmps): Add
"fccmps" type.
* config/arm/cortex-r4f.md (cortex_r4_ffariths): Likewise.
(cortex_r4_fcmpd): Add "fccmpd" type.
* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
reservation.
Here's what I had in mind when I inquired about distinguishing FCMP from
FCCMP. As you can see in the patch, Exynos is the only target that
cares about it, but I wonder if ThunderX or Xgene would too.
What do you think?
Thank you,
--
Evandro Menezes
>From d96ede48a0adb46cec1f98acfe967fce22dcc406 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.mene...@samsung.com>
Date: Mon, 4 Jan 2016 18:44:30 -0600
Subject: [PATCH] Add support for the FCCMP insn types
2016-01-04 Evandro Menezes <e.mene...@samsung.com>
gcc/
* config/aarch64/aarch64.md (fccmp): Change insn type.
(fccmpe): Likewise.
* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
* config/arm/types.md (fccmps): Add new insn type.
(fccmpd): Likewise.
* config/arm/arm1020e.md (v10_ffarith): Add "fccmp{s,d}" types.
* config/arm/cortex-a17-neon.md (cortex_a17_vfp_cmp): Likewise.
* config/arm/cortex-a5.md (cortex_a5_fpalu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
* config/arm/cortex-a7.md (cortex_a7_fpalu): Likewise.
* config/arm/cortex-a8-neon.md (cortex_a8_vfp_farith): Likewise.
* config/arm/cortex-a9.md (cortex_a9_fcmp): Likewise.
* config/arm/cortex-m7.md (cortex_m7_fpalu): Likewise.
* config/arm/marvell-pj4.md (pj4_vfp_cpy): Likewise.
* config/arm/vfp11.md (vfp_ffarith): Likewise.
* config/arm/xgene1.md (xgene1_fcmp): Likewise.
* config/arm/cortex-a15-neon.md (cortex_a15_vfp_cmps): Add "fccmps"
type.
(cortex_a15_vfp_cmpd): Add "fccmpd" type.
* config/arm/cortex-m4-fpu.md (cortex_m4_fcmps): Add "fccmps" type.
* config/arm/cortex-r4f.md (cortex_r4_ffariths): Likewise.
(cortex_r4_fcmpd): Add "fccmpd" type.
* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
---
gcc/config/aarch64/aarch64.md | 4 ++--
gcc/config/aarch64/thunderx.md | 2 +-
gcc/config/arm/arm1020e.md | 2 +-
gcc/config/arm/cortex-a15-neon.md | 4 ++--
gcc/config/arm/cortex-a17-neon.md | 2 +-
gcc/config/arm/cortex-a5.md | 2 +-
gcc/config/arm/cortex-a53.md | 3 ++-
gcc/config/arm/cortex-a57.md | 2 +-
gcc/config/arm/cortex-a7.md | 3 ++-
gcc/config/arm/cortex-a8-neon.md | 3 ++-
gcc/config/arm/cortex-a9.md | 2 +-
gcc/config/arm/cortex-m4-fpu.md | 2 +-
gcc/config/arm/cortex-m7.md | 3 ++-
gcc/config/arm/cortex-r4f.md | 4 ++--
gcc/config/arm/exynos-m1.md | 5 +++++
gcc/config/arm/marvell-pj4.md | 2 +-
gcc/config/arm/types.md | 3 +++
gcc/config/arm/vfp11.md | 2 +-
gcc/config/arm/xgene1.md | 2 +-
19 files changed, 32 insertions(+), 20 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 8b737bc..9a7ebf4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -335,7 +335,7 @@
(match_operand 5 "immediate_operand")))]
"TARGET_FLOAT"
"fccmp\\t%<s>2, %<s>3, %k5, %m4"
- [(set_attr "type" "fcmp<s>")]
+ [(set_attr "type" "fccmp<s>")]
)
(define_insn "fccmpe<mode>"
@@ -350,7 +350,7 @@
(match_operand 5 "immediate_operand")))]
"TARGET_FLOAT"
"fccmpe\\t%<s>2, %<s>3, %k5, %m4"
- [(set_attr "type" "fcmp<s>")]
+ [(set_attr "type" "fccmp<s>")]
)
;; Expansion of signed mod by a power of 2 using CSNEG.
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 922df39..058713a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -156,7 +156,7 @@
(define_insn_reservation "thunderx_fcmp" 3
(and (eq_attr "tune" "thunderx")
- (eq_attr "type" "fcmps,fcmpd"))
+ (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
"thunderx_pipe1")
(define_insn_reservation "thunderx_fmul" 6
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 7cdab57..73532a1 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -279,7 +279,7 @@
;; first execute state. We model this by using 1020a_e in the first cycle.
(define_insn_reservation "v10_ffarith" 5
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
+ (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd,fccmps,fccmpd"))
"1020a_e+v10_fmac")
(define_insn_reservation "v10_farith" 5
diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index 082ccd7..3f9ea75 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -637,12 +637,12 @@
(define_insn_reservation "cortex_a15_vfp_cmpd" 8
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "fcmpd"))
+ (eq_attr "type" "fcmpd,fccmpd"))
"ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
(define_insn_reservation "cortex_a15_vfp_cmps" 8
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "fcmps"))
+ (eq_attr "type" "fcmps,fccmps"))
"ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
(define_insn_reservation "cortex_a15_vfp_arithd" 7
diff --git a/gcc/config/arm/cortex-a17-neon.md b/gcc/config/arm/cortex-a17-neon.md
index 1385560..140fafa 100644
--- a/gcc/config/arm/cortex-a17-neon.md
+++ b/gcc/config/arm/cortex-a17-neon.md
@@ -565,7 +565,7 @@
(define_insn_reservation "cortex_a17_vfp_cmp" 4
(and (eq_attr "tune" "cortexa17")
- (eq_attr "type" "fcmps,fcmpd"))
+ (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
"ca17_asimd1+ca17_fpadd1")
(define_insn_reservation "cortex_a17_vfp_arithd" 4
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 65c12a5..b4c7283 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -170,7 +170,7 @@
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
f_cvt,f_cvtf2i,f_cvti2f,\
- fcmps, fcmpd"))
+ fcmps, fcmpd, fccmps, fccmpd"))
"cortex_a5_ex1+cortex_a5_fpadd_pipe")
;; For fconsts and fconstd, 8-bit immediate data is passed directly from
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index c1eeedb..aa76c97 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -508,7 +508,8 @@
(define_insn_reservation "cortex_a53_fpalu" 5
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
- f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
+ f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
+ f_rints, f_rintd,
f_minmaxs, f_minmaxd"))
"cortex_a53_slot_any,cortex_a53_fp_alu")
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 0d28951..f4c112c 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -716,7 +716,7 @@
(define_insn_reservation "cortex_a57_fp_cmp" 7
(and (eq_attr "tune" "cortexa57")
- (eq_attr "type" "fcmps,fcmpd"))
+ (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
"ca57_cx2")
(define_insn_reservation "cortex_a57_fp_arith" 4
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index a7ee466..a2eea0e 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -244,7 +244,8 @@
(define_insn_reservation "cortex_a7_fpalu" 4
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,\
- f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
+ f_cvt, f_cvtf2i, f_cvti2f,\
+ fcmps, fcmpd, fccmps, fccmpd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe")
;; For fconsts and fconstd, 8-bit immediate data is passed directly from
diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md
index 45f861f..aff2605 100644
--- a/gcc/config/arm/cortex-a8-neon.md
+++ b/gcc/config/arm/cortex-a8-neon.md
@@ -387,7 +387,8 @@
;; take four cycles, we pick that latency.
(define_insn_reservation "cortex_a8_vfp_farith" 4
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd"))
+ (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
+ fcmps,fcmpd,fccmps,fccmpd"))
"cortex_a8_vfp,cortex_a8_vfplite*3")
(define_insn_reservation "cortex_a8_vfp_cvt" 7
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 7905816..df2afa6 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -238,7 +238,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
(define_insn_reservation "cortex_a9_fcmp" 1
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fcmps, fcmpd"))
+ (eq_attr "type" "fcmps, fcmpd, fccmps, fccmpd"))
"ca9_issue_vfp_neon + ca9fp_add1")
;; Scheduling for the Multiply and MAC instructions.
diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md
index db02568..3e1c867 100644
--- a/gcc/config/arm/cortex-m4-fpu.md
+++ b/gcc/config/arm/cortex-m4-fpu.md
@@ -67,7 +67,7 @@
(define_insn_reservation "cortex_m4_fcmps" 1
(and (eq_attr "tune" "cortexm4")
- (eq_attr "type" "fcmps"))
+ (eq_attr "type" "fcmps,fccmps"))
"cortex_m4_ex_v")
(define_insn_reservation "cortex_m4_f_flag" 1
diff --git a/gcc/config/arm/cortex-m7.md b/gcc/config/arm/cortex-m7.md
index 71d04f0..09a0e37 100644
--- a/gcc/config/arm/cortex-m7.md
+++ b/gcc/config/arm/cortex-m7.md
@@ -126,7 +126,8 @@
(define_insn_reservation "cortex_m7_fpalu" 3
(and (eq_attr "tune" "cortexm7")
(eq_attr "type" "ffariths,ffarithd,fadds,faddd,fmov,fconsts,\
- fconstd,fcmpd,f_cvt,f_cvtf2i,f_cvti2f, fcmps,\
+ fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
+ fcmps,fcmpd,fccmps,fccmpd,\
fmuls,f_flag"))
"cm7_i0|cm7_i1,cm7_fpu")
diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md
index a34feb7..45d5116 100644
--- a/gcc/config/arm/cortex-r4f.md
+++ b/gcc/config/arm/cortex-r4f.md
@@ -53,7 +53,7 @@
(define_insn_reservation "cortex_r4_ffariths" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "ffariths,fconsts,fcmps"))
+ (eq_attr "type" "ffariths,fconsts,fcmps,fccmps"))
"cortex_r4_issue_ab+cortex_r4_issue_c+cortex_r4_v1")
(define_insn_reservation "cortex_r4_fariths" 3
@@ -141,7 +141,7 @@
(define_insn_reservation "cortex_r4_fcmpd" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "fcmpd"))
+ (eq_attr "type" "fcmpd,fccmpd"))
"cortex_r4_single_issue*2")
(define_insn_reservation "cortex_r4_f_cvt" 8
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index 0448073..973c8a9 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -823,6 +823,11 @@
(eq_attr "type" "fcmps, fcmpd"))
"em1_nmisc")
+(define_insn_reservation "exynos_m1_fp_ccmp" 7
+ (and (eq_attr "tune" "exynosm1")
+ (eq_attr "type" "fccmps, fccmpd"))
+ "em1_st, em1_nmisc")
+
(define_insn_reservation "exynos_m1_fp_sel" 4
(and (eq_attr "tune" "exynosm1")
(eq_attr "type" "fcsel"))
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index c1bc99e..5c49853 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -209,7 +209,7 @@
(define_insn_reservation "pj4_vfp_cpy" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
- fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
+ fcmps,fcmpd,fccmps,fccmpd,f_cvt,f_cvtf2i,f_cvti2f"))
"pj4_is,nothing*2,vissue,vfast,nothing*2")
;; Enlarge latency, and wish that more nondependent insns are
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 321ff89..daf7162 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -70,6 +70,7 @@
; f_rint[d,s] double/single floating point rount to integral.
; f_store[d,s] double/single store to memory. Used for VFP unit.
; fadd[d,s] double/single floating-point scalar addition.
+; fccmp[d,s] double/single floating-point conditional compare.
; fcmp[d,s] double/single floating-point compare.
; fconst[d,s] double/single load immediate.
; fcsel From ARMv8-A: Floating-point conditional select.
@@ -582,6 +583,8 @@
f_stores,\
faddd,\
fadds,\
+ fccmpd,\
+ fccmps,\
fcmpd,\
fcmps,\
fconstd,\
diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md
index 9fac4ce..1390fa1 100644
--- a/gcc/config/arm/vfp11.md
+++ b/gcc/config/arm/vfp11.md
@@ -51,7 +51,7 @@
(define_insn_reservation "vfp_ffarith" 4
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
+ (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd,fccmps,fccmpd,"))
"fmac")
(define_insn_reservation "vfp_farith" 8
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index 8dfd8a1..b7aeac6 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -154,7 +154,7 @@
(define_insn_reservation "xgene1_fcmp" 10
(and (eq_attr "tune" "xgene1")
- (eq_attr "type" "fcmpd,fcmps"))
+ (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
"xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
(define_insn_reservation "xgene1_fcsel" 3
--
1.9.1
