On 11/12/15 01:26, Segher Boessenkool wrote:
On Thu, Dec 10, 2015 at 05:05:12PM +0100, Bernd Schmidt wrote:
On 12/10/2015 03:36 PM, Kyrill Tkachov wrote:
I'm okay with delaying this for next stage 1 if people prefer, though I
think it's
pretty low risk.
I think this is something we should fix now.
I agree.
+ x = XEXP (x, 0);
+ if (start > 0)
+ x = gen_rtx_LSHIFTRT (mode, x, GEN_INT (start));
I think this should just use simplify_shift_const. gen_rtx_FOO should be
avoided.
A lot of combine does that, it really is stuck in the 80's. I wouldn't
use simplify_shift_const here, but simply simplify_gen_binary.
In change_zero_ext it also creates the final AND with gen_rtx_AND.
Perhaps that should also be changed to simplify_gen_binary.
But I haven't seen any cases where it causes trouble yet, so we
could fix it up separately.
The patch is okay with or without that change.
Thanks for the suggestions.
I'll go with simplify_gen_binary.
Here's what I'll be committing.
Thanks,
Kyrill
2015-12-10 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* combine.c (change_zero_ext): Do not create a shift of zero length.
Segher
diff --git a/gcc/combine.c b/gcc/combine.c
index 9465e5927145e768f1a5fc43ce7c3621033d8aef..8601d8983ce345e2129dd047b3520d98c0582842 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -11037,7 +11037,8 @@ change_zero_ext (rtx *src)
if (BITS_BIG_ENDIAN)
start = GET_MODE_PRECISION (mode) - size - start;
- x = gen_rtx_LSHIFTRT (mode, XEXP (x, 0), GEN_INT (start));
+ x = simplify_gen_binary (LSHIFTRT, mode,
+ XEXP (x, 0), GEN_INT (start));
}
else if (GET_CODE (x) == ZERO_EXTEND
&& GET_CODE (XEXP (x, 0)) == SUBREG
