[PATCH, i386]: Fix PR 67967, ICE in i386_pe_seh_unwind_emit

[Uros Bizjak]

Attached patch fixes PR 67967, where we emit REG_CFA_EXPRESSION,
attached to aligned SSE store. This is unnecessary, and confuses SEH
targets.

2015-10-14  Uros Bizjak  <ubiz...@gmail.com>

    PR target/67967
    * config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add
    REG_CFA_EXPRESSION to aligned SSE stores.

Bootstrapped and regression tested on x86_64-linux-gnu, also tested
with a crosscompiler to x86_64-unknown-cygwin.

Committed to mainline SVN, will be committed to gcc-5 branch.

Uros.

Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c  (revision 228818)
+++ config/i386/i386.c  (working copy)
@@ -11612,6 +11612,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, u
 {
   struct machine_function *m = cfun->machine;
   rtx reg = gen_rtx_REG (mode, regno);
+  rtx unspec = NULL_RTX;
   rtx mem, addr, base, insn;
   unsigned int align;
 
@@ -11626,13 +11627,9 @@ ix86_emit_save_reg_using_mov (machine_mode mode, u
      In case INCOMING_STACK_BOUNDARY is misaligned, we have
      to emit unaligned store.  */
   if (mode == V4SFmode && align < 128)
-    {
-      rtx unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU);
-      insn = emit_insn (gen_rtx_SET (mem, unspec));
-    }
-  else
-    insn = emit_insn (gen_rtx_SET (mem, reg));
+    unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU);
 
+  insn = emit_insn (gen_rtx_SET (mem, unspec ? unspec : reg));
   RTX_FRAME_RELATED_P (insn) = 1;
 
   base = addr;
@@ -11679,7 +11676,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, u
       mem = gen_rtx_MEM (mode, addr);
       add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, reg));
     }
-  else
+  else if (unspec)
     add_reg_note (insn, REG_CFA_EXPRESSION, gen_rtx_SET (mem, reg));
 }