On Thu, Sep 10, 2015 at 10:03 AM, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote: > Hi all, > > The ICE in this PR occurs when trying to compile code containing > half-precision FP operations > for Thumb2 with -mrestrict-it and an -mfpu that does not support fp16 > (-mfpu=neon or lower). > > The problem is that we disable for -mrestrict-it the *arm32_movhf pattern > that performs the move using only > the general regs. > > Instead what we should do is allow the pattern to match but forbid its > predication for -mrestrict-it > by using the predicable_short_it attribute. > > This fixes the ICE. > > Bootstrap and test on arm is ok. > This bug appears on the 5 and 4.9 branches as well. > Ok for all active branches if testing there comes clean?
OK if no regressions, Thanks, Ramana > > Thanks, > Kyrill > > 2015-09-10 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/67439 > * config/arm/arm.md (*arm32_movhf): Remove !arm_restrict_it from > predicate. Set predicable_short_it attr to "no". > > 2015-09-10 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/67439 > * gcc.target/arm/pr67439_1.c: New test.
