On Tue, Sep 01, 2015 at 04:04:37PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This second patch implements the new optabs for aarch64.
> The new expander is almost identical to the mov<mode>cc expander
> except that operand 2 has a neg or a not before it to reflect the
> fact that it should be negated if the comparison in operand 1 holds.
> These patterns will eventually match to the CSNEG and CSINV instructions.
>
> The test included shows the kind of code that triggers this.
> We will now create a single immediate move followed by a CSNEG (or CSINV)
> rather than performing two immediate moves followed by a CSEL.
>
> Bootstrapped and tested on aarch64-none-linux-gnu.
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index c3b985b..77bc7cd 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -3038,6 +3038,24 @@ (define_expand "mov<mode>cc"
> }
> )
>
> +(define_expand "<neg_not_op><mode>cc"
> + [(set (match_operand:GPI 0 "register_operand" "")
> + (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
> + (NEG_NOT:GPI (match_operand:GPI 2 "register_operand"
> ""))
> + (match_operand:GPI 3 "register_operand" "")))]
> + ""
> + {
> + rtx ccreg;
> + enum rtx_code code = GET_CODE (operands[1]);
> +
> + if (code == UNEQ || code == LTGT)
> + FAIL;
> +
> + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
> + XEXP (operands[1], 1));
> + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
> + }
> +)
OK. Shame we can't refactor some of this duplicate expansion code...
Thanks,
James
> 2015-09-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
>
> * config/aarch64/aarch64.md (<neg_not_op><mode>cc): New define_expand.
> * config/aarch64/iterators.md (NEG_NOT): New code iterator.
> (neg_not_op): New code attribute.
>
> 2015-09-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
>
> * gcc.target/aarch64/cond_op_imm_1.c: New test.
