On 14/08/15 14:36, Matthew Wahab wrote:
Tests for the code generated by the Aarch64 backends for the __sync and
__atomic builtins assume that they are implemented using sequences based
on load-exclusive and store-exclusive instructions. ARMv8.1 introduces
atomic instructions which can be used to implement __sync and __atomic
builtins. This means that the tests could fail if the default target is
set to a cpu that enables the atomic instructions.
This patch adjusts the tests to explicitly disable the LSE extension
providing the atomic instructions so that the compiler falls back to
generating the load-excluclusive/store-exclusive sequences.
Tested for aarch64-none-elf with cross-compiled check-gcc. Also tested
aarch64-none-elf with check-gcc using a custom build of the compiler
with LSE extensions (atomic CAS) enabled by default.
I've noticed another test that should be adjusted; it doesn't use CAS but would use
other atomic instructions. I'll respin the patch to include it.
Matthew
