Hello!
Similar to my previous patch, attached patch renames obsolete insv to
insv<mode>.
2015-07-06 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (insv<mode>): Rename from insv. Use SWI48
modes for operands 0 and 3. Use SImode for operands 2 and 3.
Copy operand 0 to a temporary if !ext_register_operand. Remove
ancient extract_bit_field workaround.
(insv<mode>_1): Rename from mov<mode>_insv_1.
(*insvqi): Rename from *movqi_insv_2.
* config/i386/i386.c (emit_i386_cw_initialization): Update calls
for renamed insvsi_1.
(promote_duplicated_reg): Ditto for renamed insv<mode>_1.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.
Uros.
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 225471)
+++ config/i386/i386.c (working copy)
@@ -17063,19 +17063,19 @@ emit_i387_cw_initialization (int mode)
{
case I387_CW_TRUNC:
/* round toward zero (truncate) */
- emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
+ emit_insn (gen_insvsi_1 (reg, GEN_INT (0xc)));
slot = SLOT_CW_TRUNC;
break;
case I387_CW_FLOOR:
/* round down toward -oo */
- emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
+ emit_insn (gen_insvsi_1 (reg, GEN_INT (0x4)));
slot = SLOT_CW_FLOOR;
break;
case I387_CW_CEIL:
/* round up toward +oo */
- emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
+ emit_insn (gen_insvsi_1 (reg, GEN_INT (0x8)));
slot = SLOT_CW_CEIL;
break;
@@ -24834,9 +24834,9 @@ promote_duplicated_reg (machine_mode mode, rtx val
if (!TARGET_PARTIAL_REG_STALL)
if (mode == SImode)
- emit_insn (gen_movsi_insv_1 (reg, reg));
+ emit_insn (gen_insvsi_1 (reg, reg));
else
- emit_insn (gen_movdi_insv_1 (reg, reg));
+ emit_insn (gen_insvdi_1 (reg, reg));
else
{
tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 225471)
+++ config/i386/i386.md (working copy)
@@ -2780,7 +2780,37 @@
(const_string "SI")
(const_string "QI")))])
-(define_insn "mov<mode>_insv_1"
+(define_expand "insv<mode>"
+ [(set (zero_extract:SWI48 (match_operand:SWI48 0 "register_operand")
+ (match_operand:SI 1 "const_int_operand")
+ (match_operand:SI 2 "const_int_operand"))
+ (match_operand:SWI48 3 "register_operand"))]
+ ""
+{
+ rtx dst;
+
+ if (ix86_expand_pinsr (operands))
+ DONE;
+
+ /* Handle insertions to %ah et al. */
+ if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
+ FAIL;
+
+ dst = operands[0];
+
+ if (!ext_register_operand (dst, VOIDmode))
+ dst = copy_to_reg (dst);
+
+ emit_insn (gen_insv<mode>_1 (dst, operands[3]));
+
+ /* Fix up the destination if needed. */
+ if (dst != operands[0])
+ emit_move_insn (operands[0], dst);
+
+ DONE;
+})
+
+(define_insn "insv<mode>_1"
[(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "+Q,Q")
(const_int 8)
(const_int 8))
@@ -2795,7 +2825,7 @@
(set_attr "type" "imov")
(set_attr "mode" "QI")])
-(define_insn "*movqi_insv_2"
+(define_insn "*insvqi"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
@@ -10608,34 +10638,6 @@
;; Bit set / bit test instructions
-(define_expand "insv"
- [(set (zero_extract (match_operand 0 "register_operand")
- (match_operand 1 "const_int_operand")
- (match_operand 2 "const_int_operand"))
- (match_operand 3 "register_operand"))]
- ""
-{
- rtx (*gen_mov_insv_1) (rtx, rtx);
-
- if (ix86_expand_pinsr (operands))
- DONE;
-
- /* Handle insertions to %ah et al. */
- if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
- FAIL;
-
- /* From mips.md: insert_bit_field doesn't verify that our source
- matches the predicate, so check it again here. */
- if (! ext_register_operand (operands[0], VOIDmode))
- FAIL;
-
- gen_mov_insv_1 = (TARGET_64BIT
- ? gen_movdi_insv_1 : gen_movsi_insv_1);
-
- emit_insn (gen_mov_insv_1 (operands[0], operands[3]));
- DONE;
-})
-
;; %%% bts, btr, btc, bt.
;; In general these instructions are *slow* when applied to memory,
;; since they enforce atomic operation. When applied to registers,
