2015-06-04 Uros Bizjak <ubiz...@gmail.com>
PR target/66369
* config/i386/sse.md (<sse2_avx2>_pmovmsk): Merge from avx2_pmovmskb
and sse2_pmovmskb using VI1_AVX2 mode iterator.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): New insn pattern.
(*<sse2_avx2>_pmovmskb_zext): Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 224114)
+++ config/i386/sse.md (working copy)
@@ -13112,27 +13112,51 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
-(define_insn "avx2_pmovmskb"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V32QI 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
- "TARGET_AVX2"
- "vpmovmskb\t{%1, %0|%0, %1}"
+(define_insn "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (unspec:SI
+ [(match_operand:VF_128_256 1 "register_operand" "x")]
+ UNSPEC_MOVMSK)))]
+ "TARGET_64BIT && TARGET_SSE"
+ "%vmovmsk<ssemodesuffix>\t{%1, %k0|%k0, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DI")])
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "<MODE>")])
-(define_insn "sse2_pmovmskb"
+(define_insn "<sse2_avx2>_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
+ (unspec:SI
+ [(match_operand:VI1_AVX2 1 "register_operand" "x")]
+ UNSPEC_MOVMSK))]
"TARGET_SSE2"
"%vpmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix_data16" "1")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (match_test "TARGET_AVX")
+ (const_string "*")
+ (const_string "1")))
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
+(define_insn "*<sse2_avx2>_pmovmskb_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (unspec:SI
+ [(match_operand:VI1_AVX2 1 "register_operand" "x")]
+ UNSPEC_MOVMSK)))]
+ "TARGET_64BIT && TARGET_SSE2"
+ "%vpmovmskb\t{%1, %k0|%k0, %1}"
+ [(set_attr "type" "ssemov")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (match_test "TARGET_AVX")
+ (const_string "*")
+ (const_string "1")))
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "SI")])
+
(define_expand "sse2_maskmovdqu"
[(set (match_operand:V16QI 0 "memory_operand")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand")
