The compiler currently ICEs when compiling a stdarg function with
+nofp, as reported in PR 66258.
The aarch64.md file disables FP instructions using TARGET_FLOAT, which
supports both -mgeneral-regs-only and +nofp. But there is code in
aarch64.c that checks TARGET_GENERAL_REGS_ONLY. This results in FP
instructions when using +nofp, The aarch64.c code needs to use
TARGET_FLOAT instead like the md file already does.
I can't meaningfully test this with a bootstrap, since the patch has
no effect unless I bootstrap with +nofp, and that will fail as gcc
contains floating point code.
The testsuite already has multiple stdarg tests, so there is no need
for another one.
I tested this by verifying I get the same results for some simple
testcasess with and without the patch, with and without using
-mgeneral-regs-only and -mcpu=cortex-a53+nofp.
2015-05-22 Jim Wilson <jim.wil...@linaro.org>
PR target/66258
* config/aarch64/aarch64.c (aarch64_function_value_regno_p): Change
!TARGET_GENERAL_REGS_ONLY to TARGET_FLOAT.
(aarch64_secondary_reload): Likewise
(aarch64_expand_builtin_va_start): Change TARGET_GENERAL_REGS_ONLY
to !TARGET_FLOAT.
(aarch64_gimplify_va_arg_expr, aarch64_setup_incoming_varargs):
Likewise.
Index: config/aarch64/aarch64.c
===================================================================
--- config/aarch64/aarch64.c (revision 223590)
+++ config/aarch64/aarch64.c (working copy)
@@ -1666,7 +1666,7 @@ aarch64_function_value_regno_p (const un
/* Up to four fp/simd registers can return a function value, e.g. a
homogeneous floating-point aggregate having four members. */
if (regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS)
- return !TARGET_GENERAL_REGS_ONLY;
+ return TARGET_FLOAT;
return false;
}
@@ -4783,7 +4783,7 @@ aarch64_secondary_reload (bool in_p ATTR
/* A TFmode or TImode memory access should be handled via an FP_REGS
because AArch64 has richer addressing modes for LDR/STR instructions
than LDP/STP instructions. */
- if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS
+ if (TARGET_FLOAT && rclass == GENERAL_REGS
&& GET_MODE_SIZE (mode) == 16 && MEM_P (x))
return FP_REGS;
@@ -7571,7 +7571,7 @@ aarch64_expand_builtin_va_start (tree va
vr_save_area_size
= (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG;
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
{
if (cum->aapcs_nvrn > 0)
sorry ("%qs and floating point or vector arguments",
@@ -7681,7 +7681,7 @@ aarch64_gimplify_va_arg_expr (tree valis
&is_ha))
{
/* TYPE passed in fp/simd registers. */
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
sorry ("%qs and floating point or vector arguments",
"-mgeneral-regs-only");
@@ -7918,7 +7918,7 @@ aarch64_setup_incoming_varargs (cumulati
gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn;
vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn;
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
{
if (local_cum.aapcs_nvrn > 0)
sorry ("%qs and floating point or vector arguments",
