This adds a test of vcvt_f32_f16 and vcvt_f16_f32, also vcvt_high_f32_f16 and
vcvt_high_f16_f32.
On ARM, we pass additional option -mfpu=neon-fp16 to the compiler (possible
following patch 2/3). The compiler is already receiving an option such as
-mfpu=neon or -mfpu=crypto-neon-fp-armv8, but passing neon-fp16 as well as
either of those appears to do no harm, and turns on the superset of all -mfpu
options, as desired.
On AArch64, we additionally test vcvt_high_f32_f16 and vcvt_high_f16_f32; these
are not tested on ARM as the relevant intrinsics do not exist in 32-bit state.
Passing on aarch64_be-none-elf, aarch64-none-elf, arm-none-linux-gnueabi,
aarch64-none-linux-gnu.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..a346b3d72e13d5b2028de5ae7b88f910dcb3f862
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
@@ -0,0 +1,96 @@
+/* { dg-additional-options "-mfpu=neon-fp16" { target { arm*-*-* } } } */
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+#include <math.h>
+
+/* Expected results for vcvt. */
+VECT_VAR_DECL (expected,hfloat,32,4) [] = { 0x41800000, 0x41700000,
+ 0x41600000, 0x41500000 };
+VECT_VAR_DECL (expected,hfloat,16,4) [] = { 0x3e00, 0x4100, 0x4300, 0x4480 };
+
+/* Expected results for vcvt_high_f32_f16. */
+VECT_VAR_DECL (expected_high,hfloat,32,4) [] = { 0xc1400000, 0xc1300000,
+ 0xc1200000, 0xc1100000 };
+/* Expected results for vcvt_high_f16_f32. */
+VECT_VAR_DECL (expected_high,hfloat,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000,
+ 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+
+void
+exec_vcvt (void)
+{
+#define TEST_MSG vcvt_f32_f16
+ {
+ VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 };
+
+ DECL_VARIABLE (vector_src, float, 16, 4);
+
+ VLOAD (vector_src, buffer_src, , float, f, 16, 4);
+ DECL_VARIABLE (vector_res, float, 32, 4) =
+ vcvt_f32_f16 (VECT_VAR (vector_src, float, 16, 4));
+ vst1q_f32 (VECT_VAR (result, float, 32, 4),
+ VECT_VAR (vector_res, float, 32, 4));
+
+ CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ }
+#undef TEST_MSG
+
+ clean_results ();
+
+#define TEST_MSG vcvt_f16_f32
+ {
+ VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 };
+ DECL_VARIABLE (vector_src, float, 32, 4);
+
+ VLOAD (vector_src, buffer_src, q, float, f, 32, 4);
+ DECL_VARIABLE (vector_res, float, 16, 4) =
+ vcvt_f16_f32 (VECT_VAR (vector_src, float, 32, 4));
+ vst1_f16 (VECT_VAR (result, float, 16, 4),
+ VECT_VAR (vector_res, float, 16 ,4));
+
+ CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, "");
+ }
+#undef TEST_MSG
+
+#ifdef __ARM_64BIT_STATE
+ clean_results ();
+
+#define TEST_MSG "vcvt_high_f32_f16"
+ {
+ DECL_VARIABLE (vector_src, float, 16, 8);
+ VLOAD (vector_src, buffer, q, float, f, 16, 8);
+ DECL_VARIABLE (vector_res, float, 32, 4);
+ VECT_VAR (vector_res, float, 32, 4) =
+ vcvt_high_f32_f16 (VECT_VAR (vector_src, float, 16, 8));
+ vst1q_f32 (VECT_VAR (result, float, 32, 4),
+ VECT_VAR (vector_res, float, 32, 4));
+ CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected_high, "");
+ }
+#undef TEST_MSG
+ clean_results ();
+
+#define TEST_MSG "vcvt_high_f16_f32"
+ {
+ DECL_VARIABLE (vector_low, float, 16, 4);
+ VDUP (vector_low, , float, f, 16, 4, 2.0);
+
+ DECL_VARIABLE (vector_src, float, 32, 4);
+ VLOAD (vector_src, buffer, q, float, f, 32, 4);
+
+ DECL_VARIABLE (vector_res, float, 16, 8) =
+ vcvt_high_f16_f32 (VECT_VAR (vector_low, float, 16, 4),
+ VECT_VAR (vector_src, float, 32, 4));
+ vst1q_f16 (VECT_VAR (result, float, 16, 8),
+ VECT_VAR (vector_res, float, 16, 8));
+
+ CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_high, "");
+ }
+#endif
+}
+
+int
+main (void)
+{
+ exec_vcvt ();
+ return 0;
+}
