On Fri, Apr 03, 2015 at 07:19:24PM +0000, dje at gcc dot gnu.org wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65614
> 
> --- Comment #4 from David Edelsohn <dje at gcc dot gnu.org> ---
> Comment on attachment 35227
>   --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35227
> Proposed patch to fix the problem
> 
> The FLOAT_EXTEND cost should be based on the processor tuning, not the ISA.

This patch moves the decision to the cost structure based on the processor
tuning.  Is it ok to install?

[gcc]
2015-04-06  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        PR target/65614
        * config/rs6000/rs6000.c (struct processor_costs): Add cost field
        for SF->DF conversions to make FLOAT_EXTEND more expensive, so
        that LFD is used to load double constants instead of LFS.  Add
        defaults for all costs structures.  Add comments for missing
        initialization fields.
        (size32_cost): Likewise.
        (size64_cost): Likewise.
        (rs64a_cost): Likewise.
        (mpccore_cost): Likewise.
        (ppc403_cost): Likewise.
        (ppc405_cost): Likewise.
        (ppc440_cost): Likewise.
        (ppc476_cost): Likewise.
        (ppc601_cost): Likewise.
        (ppc603_cost): Likewise.
        (ppc604_cost): Likewise.
        (ppc604e_cost): Likewise.
        (ppc620_cost): Likewise.
        (ppc630_cost): Likewise.
        (ppccell_cost): Likewise.
        (ppc750_cost): Likewise.
        (ppc7450_cost): Likewise.
        (ppc8540_cost): Likewise.
        (ppce300c2c3_cost): Likewise.
        (ppce500mc_cost): Likewise.
        (ppce500mc64_cost): Likewise.
        (ppce5500_cost): Likewise.
        (ppce6500_cost): Likewise.
        (titan_cost): Likewise.
        (power4_cost): Likewise.
        (power6_cost): Likewise.
        (power7_cost): Likewise.
        (power8_cost): Likewise.
        (ppca2_cost): Likewise.
        (rs6000_rtx_costs): Make FLOAT_EXTEND use SFDF_convert field.

        * config/rs6000/rs6000.md (extendsfdf2_fpr): Generate XSCPSGNDP
        instead of XXLOR to copy SFmode to clear out dirty bits created
        when SFmode denormals are generated.
        (mov<mode>_hardfloat, FMOVE32 case): Likewise.
        (truncdfsf2_fpr): Add support for ISA 2.07 XSRSP instruction.

[gcc/testsuite]
2015-04-06  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        PR target/65614
        * gcc.target/powerpc/compress-float-ppc-pic.c: Run test on power5
        to get floating point compression.
        * gcc.target/powerpc/compress-foat-ppc.c: Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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