On Fri, Apr 3, 2015 at 4:09 PM, James Greenhalgh
<james.greenha...@arm.com> wrote:
> On Fri, Apr 03, 2015 at 07:53:12PM +0100, Ramana Radhakrishnan wrote:
>> On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <seb...@gmail.com> wrote:
>> > Hi,
>> >
>> > On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
>> > <james.greenha...@arm.com> wrote:
>> >> Trunk is currently in Stage 4 development, these patches are fairly
>> >> low-risk, but they are certainly not regression fixes. I'll defer
>> >> to port maintainers and release managers for the final say, but in my
>> >> opinion it would not be appropriate to commit them until Stage 1
>> >> development for GCC 6.0 opens (hopefully in a few weeks).
>> >
>> > I thought that adding flags for new processors was ok at any time,
>> > even to backport.
>>
>> It's usually risk vs reward on a per patch basis and I don't think of
>> it as a general rule. We've always avoided the CPU tuning backport
>> rule to the FSF branches. The smaller the CPU tuning patch - the
>> better it is and in this case I'm comfortable with the patch going in
>> as it is adding another tuning option, using existing constructs and
>> is not invasive in the backend.
>
> Thanks for the clarification Ramana.
>
> In which case, and now that I've seen that binutils support has also
> been accepted, the AArch64 part is OK to commit (assuming no regressions
> and no objections from Richard or Jakub).
I will wait to hear from Richi or Jakub before committing the two patches.
>
> It would be great if you could follow these up with a patch for
> changes.html for GCC 5 for both ARM and AArch64.
Attached. I will commit this after the two patches adding the exynos-m1 flags.
Thanks,
Sebastian
*** changes.html.~1.92.~ 2015-03-27 09:42:10.000000000 -0500
--- changes.html 2015-04-03 21:57:33.550001606 -0500
***************
*** 585,591 ****
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53
(<code>cortex-a72.cortex-a53</code>),
Cavium ThunderX (<code>thunderx</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>).
The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
--- 585,591 ----
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53
(<code>cortex-a72.cortex-a53</code>),
Cavium ThunderX (<code>thunderx</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>), and Samsung Exynos M1 (<code>exynos-m1</code>).
The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
***************
*** 624,630 ****
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53
(<code>cortex-a72.cortex-a53</code>),
ARM Cortex-M7 (<code>cortex-m7</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>). The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
<code>-mtune=cortex-a72.cortex-a53</code>.
--- 624,631 ----
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53
(<code>cortex-a72.cortex-a53</code>),
ARM Cortex-M7 (<code>cortex-m7</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>), and Samsung Exynos M1 (<code>exynos-m1</code>).
! The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
<code>-mtune=cortex-a72.cortex-a53</code>.
