This patch fixes PR target/64205, which was caused due to my previous patch to
add the -mupper-regs support for scalar floating point to occupy the VSX
floating point registers that are overlaid on top of the traditional Altivec
registers, starting with ISA 2.06 (power7).
The problem was, I added secondary reload handlers for SDmode unconditionally.
On systems before ISA 2.06, there are no stores and loads for 32-bit SDmode in
a floating point register, and so you can't do normal secondary reload
operations on this (you have to do a 64-bit store and a 32-bit load on the
bottom bits).
I have tested this with a full bootstrap on PowerPC 64-bit systems with no
regressions. In addition, I built a bootstrap compiler using the --with-cpu=G5
option and it succeeded. Is it ok to install the patches in trunk, and in any
branches that the upper regs patches were applied to?
[gcc]
2015-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/64205
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not
add a general secondary reload handler for SDmode, unless we have
both read/write support for SDmode.
[gcc/testsuite]
2015-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/64205
* gcc.target/powerpc/pr64205.c: New file.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 220460)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2849,8 +2849,15 @@ rs6000_init_hard_regno_mode_ok (bool glo
reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
- reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
- reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
+
+ /* If we don't have the load/store integer instructions, don't use
+ the general reload mechanisms for SDmode, which must be handled
+ specially. */
+ if (TARGET_NO_SDMODE_STACK)
+ {
+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
+ }
if (TARGET_VSX_TIMODE)
{
@@ -2903,8 +2910,15 @@ rs6000_init_hard_regno_mode_ok (bool glo
reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
- reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
- reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
+
+ /* If we don't have the load/store integer instructions, don't use
+ the general reload mechanisms for SDmode, which must be handled
+ specially. */
+ if (TARGET_NO_SDMODE_STACK)
+ {
+ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
+ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
+ }
if (TARGET_VSX_TIMODE)
{
Index: gcc/testsuite/gcc.target/powerpc/pr64205.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr64205.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr64205.c (revision 0)
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=G5" } } */
+/* { dg-options "-O2 -mcpu=G5 -maltivec -m32" } */
+
+union ieee754r_Decimal32
+{
+ _Decimal32 sd;
+ unsigned int cc0;
+};
+
+unsigned int
+__decoded32 (_Decimal32 a)
+{
+ union ieee754r_Decimal32 d;
+ d.sd = a;
+ return d.cc0;
+}
