On 01/15/15 01:13, Jakub Jelinek wrote:
The glibc barriers are supposedly something that can be CSEd (one barrier
instead of
two consecutive barriers is enough), but certainly not moved across any
loads/stores
in between. In the kernel case, the enable/disable probably wouldn't allow
even CSE.
So I'm with Jeff that we should treat "memory" at least as unspecified read and
write,
and whether we can CSE them if there are no memory loads/stores in between them
can
be discussed (most likely the kernel would be safe even in that case, because
those
usually don't nest and appear in pairs, or act as barriers (like the glibc
case),
or read from segment registers (guess again ok to be CSEd with no intervening
loads/stores).
In 4.9 backport I'd prefer not to CSE them at all though, stay conservative.
My vote would be to go conservative. For gcc6 consider allowing a
"memory" tag in the inputs and outputs to specify a read of any memory
location and write of any memory location respectively. A "memory" tag
in the clobbers would maintain the conservative behaviour.
jeff
