On 28 June 2011 15:20, Ramana Radhakrishnan
<ramana.radhakrish...@linaro.org> wrote:
> Hi,
>
> Sometime back Chung-Lin noticed that a few of the VFP patterns as below
> had the '+' constraint modifiers rather than the '=' constraint
> modifiers.
>
> I've now corrected this as follows and tested this on trunk with
> arm-linux-gnueabi
> and qemu for a v7-a neon test run. Committed.
I just noticed that the patch that I sent out had an unrelated change
to arm.h while what I actually tested and committed was
without that hunk. Attached is what I actually committed.
Phew.
cheers
Ramana
2011-06-28 Ramana Radhakrishnan <ramana.radhakrish...@linaro.org>
* config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
with '=' constraint modifier.
(*divdf3_vfp): Likewise.
("*mulsf3_vfp"): Likewise.
("*muldf3_vfp"): Likewise.
("*mulsf3negsf_vfp"): Likewise.
("*muldf3negdf_vfp"): Likewise.
Index: gcc/config/arm/vfp.md
===================================================================
--- gcc/config/arm/vfp.md (revision 175585)
+++ gcc/config/arm/vfp.md (working copy)
@@ -719,7 +719,7 @@
;; Division insns
(define_insn "*divsf3_vfp"
- [(set (match_operand:SF 0 "s_register_operand" "+t")
+ [(set (match_operand:SF 0 "s_register_operand" "=t")
(div:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -729,7 +729,7 @@
)
(define_insn "*divdf3_vfp"
- [(set (match_operand:DF 0 "s_register_operand" "+w")
+ [(set (match_operand:DF 0 "s_register_operand" "=w")
(div:DF (match_operand:DF 1 "s_register_operand" "w")
(match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -742,7 +742,7 @@
;; Multiplication insns
(define_insn "*mulsf3_vfp"
- [(set (match_operand:SF 0 "s_register_operand" "+t")
+ [(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -752,7 +752,7 @@
)
(define_insn "*muldf3_vfp"
- [(set (match_operand:DF 0 "s_register_operand" "+w")
+ [(set (match_operand:DF 0 "s_register_operand" "=w")
(mult:DF (match_operand:DF 1 "s_register_operand" "w")
(match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -761,9 +761,8 @@
(set_attr "type" "fmuld")]
)
-
(define_insn "*mulsf3negsf_vfp"
- [(set (match_operand:SF 0 "s_register_operand" "+t")
+ [(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
(match_operand:SF 2 "s_register_operand" "t")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -773,7 +772,7 @@
)
(define_insn "*muldf3negdf_vfp"
- [(set (match_operand:DF 0 "s_register_operand" "+w")
+ [(set (match_operand:DF 0 "s_register_operand" "=w")
(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
(match_operand:DF 2 "s_register_operand" "w")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
