On 06/23/11 16:34, Andrew Stubbs wrote: > The patches provide a number of improvements: > > * Support for instructions that widen by more than one mode > (e.g. from HImode to DImode). > > * Use of widening multiplies even when the input mode is narrower than > the instruction uses. (e.g. Use HI->DI to do QI->DI). > > * Use of signed widening multiplies (of a larger mode) where unsigned > multiplies are not available. > > * Support for input operands with mis-matched signedness, with or > without usmul_widen_optab. > > * Support for input operands with mis-matched mode [1]. > > * Improved pattern matching in the widening_mult pass. > * Recognition of true types, even if obscured by a cast. > * Insertion of extra gimple statements where the existing code was > incompatible with widening multiplies. > * Recognition of widening multiply-and-accumulate even where the > multiply expression was not widening.
That all sounds good, but missing from this list is something that occurs on many CPUs - widening from the high part of a register. The current machinery only recognizes lowxlow widening multiplication, but hardware often exists for highxlow and highxhigh. For example, Blackfin has "<su_optab>hisi_lh"/hl/hh instruction patterns; C6X also has a full set; ARM has mulhisi3tb/bt/tt. Do you think it will be possible to extend your new framework to handle this case as well? Bernd
