Hi,
It turns out that my effort last week in canonicalizing the vbic and
the vorn patterns in the neon bug exposed a latent bug while
bootstrapping trunk with Neon which Michael's tester picked up.. The
splitting is slightly tricky because in T2 state you've got the orn
instruction but in ARM state you don't .
I intend to follow this up with a separate patch that turns some of
these patterns off on the A8 in line with the other patches that have
come in recently to do. Before doing that I also need to reorganize
the arch attributes a bit and move the a8 and nota8 bits into a
separate attribute - so that's the matter of another patch.
Verified that the compiler passes bootstrap in both ARM and Thumb2
states . Regression tests are still running. It will be committed
after tests finish.
cheers
Ramana
2011-05-31 Ramana Radhakrishnan <ramana.radhakrish...@linaro.org>
* config/arm/neon.md (orndi3_neon): Actually split it.
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md (revision 174266)
+++ gcc/config/arm/neon.md (working copy)
@@ -801,17 +801,44 @@
[(set_attr "neon_type" "neon_int_1")]
)
-(define_insn "orndi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
- (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))
- (match_operand:DI 1 "s_register_operand" "w,r,0")))]
+;; TODO: investigate whether we should disable
+;; this and bicdi3_neon for the A8 in line with the other
+;; changes above.
+(define_insn_and_split "orndi3_neon"
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?=&r,?&r")
+ (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r"))
+ (match_operand:DI 1 "s_register_operand" "w,r,r,0")))]
"TARGET_NEON"
"@
vorn\t%P0, %P1, %P2
#
+ #
#"
- [(set_attr "neon_type" "neon_int_1,*,*")
- (set_attr "length" "*,8,8")]
+ "reload_completed &&
+ (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))"
+ [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
+ (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
+ "
+ {
+ if (TARGET_THUMB2)
+ {
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[2]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ operands[5] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ }
+ else
+ {
+ emit_insn (gen_one_cmpldi2 (operands[0], operands[2]));
+ emit_insn (gen_iordi3 (operands[0], operands[1], operands[0]));
+ DONE;
+ }
+ }"
+ [(set_attr "neon_type" "neon_int_1,*,*,*")
+ (set_attr "length" "*,16,8,8")
+ (set_attr "arch" "any,a,t2,t2")]
)
(define_insn "bic<mode>3_neon"
