On 05/25/2011 04:32 PM, H.J. Lu wrote:
> On Wed, May 25, 2011 at 8:27 AM, Richard Guenther
> <richard.guent...@gmail.com> wrote:
>> On Wed, May 25, 2011 at 5:20 PM, Michael Matz <m...@suse.de> wrote:
>>> Hi,
>>>
>>> On Wed, 25 May 2011, Richard Guenther wrote:
>>>
>>>>>> asm volatile ("" : : : "memory") in fact will work as a full memory
>>>>>> barrier
>>>>>
>>>>> How? You surely need MFENCE or somesuch, unless all you care about is
>>>>> a compiler barrier. That's what I think needs to be clarified.
>>>>
>>>> Well, yes, I'm talking about the compiler memory barrier.
>>>
>>> Something that we conventionally call "optimization barrier" :) memory
>>> barrier has a fixed meaning which we shouldn't use in this case, it's
>>> confusing.
>>
>> Sure ;)
>>
>> And to keep the info in a suitable thread what I'd like to improve here
>> is to make us disambiguate memory loads/stores against asms that
>> have no memory outputs/inputs.
>>
>
> Please let me know how I should improve the document,
"Compiler memory barrier" seems to be well-understood. I suggest
+Generates the @code{pause} machine instruction with a compiler memory barrier.
It's clear enough.
Andrew.
