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On 04/04/11 15:07, Eric Botcazou wrote:
> commit_edge_insertions contains this kludge:
>
> /* In the old rtl CFG API, it was OK to insert control flow on an
> edge, apparently? In cfglayout mode, this will *not* work, and
> the caller is responsible for making sure that control flow is
> valid at all times. */
> if (current_ir_type () == IR_RTL_CFGLAYOUT)
> return;
>
> blocks = sbitmap_alloc (last_basic_block);
> sbitmap_zero (blocks);
> FOR_EACH_BB (bb)
> if (bb->aux)
> {
> SET_BIT (blocks, bb->index);
> /* Check for forgotten bb->aux values before commit_edge_insertions
> call. */
> gcc_assert (bb->aux == &bb->aux);
> bb->aux = NULL;
> }
> find_many_sub_basic_blocks (blocks);
> sbitmap_free (blocks);
>
>
> At least on x86/x86-64, there is apparently only one case where control flow
> insns are inserted on edges: when the prologue is inserted on the entry edge.
> Once this is accounted for, the above kludge can be removed, provided that
> the
> force_nonfallthru RTL routine is enhanced to preserve the loop nest structure.
> The result is the attached patch, bootstrapped/regtested on x86 and x86-64.
>
> I'll be testing it on IA-64 and SPARC over the next few days if there is an
> agreement that this is a progress.
What about when we have a PHI, which we eliminate by inserting insns on
edges and those insns actually form a loop? You can see an example of
this in PR48389.
I'm not terribly familiar with any of this cfg code these days, so there
may be a reason why this isn't going to be a problem that I'm not aware
of. I just happened to be looking at 48389 and remembered your RFC.
jeff
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