Hi Carrot,
How about adding an alternative only enabled for T2 that uses the `l'
constraint and inventing new constraints for some of the constant values
that are valid for 16 bit instructions since the `I' and `L' constraints
have different meanings depending on whether TARGET_32BIT is valid or not ?
We could then set the value of the length attribute accordingly. I don't
think we can change the meaning of the I and L constraints very easily given
the amount of churn that might be needed
You are right. Now the logic is much clearer by splitting the constraints.
Sorry I wasn't too clear .
What I meant was to use the "enabled" trick and enable this only when
Thumb2 is enabled in the compiler.
So what you could do instead is add the alternative and then use the
arch attribute to enable this only for Thumb2.
i.e.
(define_insn "*arm_cmpsi_insn"
[(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
- (match_operand:SI 1 "arm_add_operand" "rI,L")))]
+ (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r")
+ (match_operand:SI 1 "arm_add_operand" "Py,r,I,L")))]
"TARGET_32BIT"
"@
cmp%?\\t%0, %1
+ cmp%?\\t%0, %1
+ cmp%?\\t%0, %1
cmn%?\\t%0, #%n1"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
(set_attr "arch" "t2, any")
(set_attr "length" "2, 4")]
Does that look any better ? That way you can now safely add options on a
per arch basis and reduce the amount of complexity for some of these
length calculations.
I don't think this and the other conditional branch instruction
changes are correct. This could end up being the last instruction in an IT
block and will automatically end up getting the 32 bit encoding and end up
causing trouble with the length calculations. Remember the 16 bit encoding
for the conditional instruction can't be used as the last instruction in an
IT block.
According to arm architecture reference manual, chapter A8.6.16, neither 16 bit
nor 32 bit conditional branch can be used in IT block. Only unconditional branch
can be used as the last instruction in IT block, and it isn't related
to instruction
length. So we don't need to care about branch instruction encoding in IT block.
Yes I think you are right in this case. The reason I think I
misinterpreted this was ofcourse the fact that conditional branches as
the last instruction in the ARM-ARM. I don't know why I misread it last
night.
cheers
Ramana
