https://gcc.gnu.org/g:328d29aa3df4106b919e5faaa9693ebf6ab21e3c
commit 328d29aa3df4106b919e5faaa9693ebf6ab21e3c Author: Vijay Shankar <[email protected]> Date: Thu Jul 9 05:08:01 2026 -0500 rs6000: Add support for movxo and update %A printer Split movxo between dmf and nondmf patterns. The dmf alternative emits extract and insert 512 instuctions. update %A printer to emit dmr registers. when dmr is enabled. 2026-07-09 Vijay shankar <[email protected]> Diff: --- gcc/config/rs6000/mma.md | 33 +++++++++++++++++++++++++++++---- gcc/config/rs6000/rs6000.cc | 14 +++++++++++++- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index d6e9c8b6101e..f9fb18e0c137 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -416,10 +416,10 @@ gcc_assert (false); }) -(define_insn_and_split "*movxo" - [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d") - (match_operand:XO 1 "input_operand" "ZwO,d,d"))] - "TARGET_MMA +(define_insn_and_split "*movxo_nodmf" + [(set (match_operand:XO 0 "nonimmediate_operand" "=wD,ZwO,wD") + (match_operand:XO 1 "input_operand" "ZwO,wD,wD"))] + "TARGET_MMA && !TARGET_DMF && (gpc_reg_operand (operands[0], XOmode) || gpc_reg_operand (operands[1], XOmode))" "@ @@ -436,6 +436,31 @@ (set_attr "length" "*,*,16") (set_attr "max_prefixed_insns" "2,2,*")]) +(define_insn_and_split "*movxo_dmf" + [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,ZwO,wa,wD,wD,wa") + (match_operand:XO 1 "input_operand" "ZwO,wa, wa,wa,wD,wD"))] + "TARGET_DMF + && (gpc_reg_operand (operands[0], XOmode) + || gpc_reg_operand (operands[1], XOmode))" + "@ + # + # + # + dmxxinstdmr512 %0,%x1,%Y1,0 + dmmr %0,%1 + dmxxextfdmr512 %x0,%Y0,%1,0" + "&& reload_completed + && !dmr_register_operand (operands[0], XOmode) + && !dmr_register_operand (operands[1], XOmode)" + [(const_int 0)] +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "type" "vecload,vecstore,veclogical,dmf,dmf,dmf") + (set_attr "length" "*,*,16,*,*,*") + (set_attr "max_prefixed_insns" "2,2,*,*,*,*")]) + (define_expand "vsx_assemble_pair" [(match_operand:OO 0 "vsx_register_operand") (match_operand:V16QI 1 "mma_assemble_input_operand") diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0cace93fedda..c212a6aa114a 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -8750,7 +8750,7 @@ reg_offset_addressing_ok_p (machine_mode mode) return TARGET_MMA || TARGET_DMF; case E_TDOmode: -+ return TARGET_DMF; + return TARGET_DMF; case E_SDmode: /* If we can do direct load/stores of SDmode, restrict it to reg+reg @@ -14253,6 +14253,18 @@ print_operand (FILE *file, rtx x, int code) case 'A': /* Write the MMA accumulator number associated with VSX register X. */ + if (TARGET_DMF) + { + if (!REG_P (x) || !DMR_REGNO_P (REGNO (x))) + output_operand_lossage ("invalid %%A value"); + else +#ifdef TARGET_REGNAMES + fprintf (file, "%%dm%d", (REGNO (x) - FIRST_DMR_REGNO)); +#else + fprintf (file, "%d", (REGNO (x) - FIRST_DMR_REGNO)); +#endif + return; + } if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0) output_operand_lossage ("invalid %%A value"); else
