https://gcc.gnu.org/g:05c929c143c5dea121e78092a1eaad9a422022a9
commit r17-2270-g05c929c143c5dea121e78092a1eaad9a422022a9 Author: Jim Lin <[email protected]> Date: Wed Jul 8 17:56:19 2026 -0600 [PATCH] RISC-V: Enable TARGET_SFB_ALU for andes-45-series Enable short forward branch (SFB) ALU support for the andes-45-series tune, matching the existing sfb_alu scheduling reservation already present in andes-45-series.md. gcc/ChangeLog: * config/riscv/riscv.h (TARGET_SFB_ALU): Add andes_45_series. Diff: --- gcc/config/riscv/riscv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index d72c06ec37f1..7eb85d654a7e 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -974,7 +974,8 @@ extern enum riscv_cc get_riscv_cc (const rtx use); #define TARGET_SFB_ALU \ ((riscv_microarchitecture == sifive_7) \ || (riscv_microarchitecture == sifive_p400) \ - || (riscv_microarchitecture == sifive_p600)) + || (riscv_microarchitecture == sifive_p600) \ + || (riscv_microarchitecture == andes_45_series)) /* True if the target supports misaligned vector loads and stores. */ #define TARGET_VECTOR_MISALIGN_SUPPORTED \
