https://gcc.gnu.org/g:ffd6cf2b601b586bbd30d6d2c351568fb50de148
commit ffd6cf2b601b586bbd30d6d2c351568fb50de148 Author: Kishan Parmar <[email protected]> Date: Wed Jul 8 16:31:55 2026 +0530 rs6000: Enable OOmode, VSX pair patterns and fix xxmfacc fold for TARGET_DMF Allow movoo, vsx_assemble_pair, vsx_disassemble_pair and mma_assemble_acc to fire under TARGET_DMF since the DMF expand paths internally use OOmode VSX pair temporaries when inserting data into DMRs. Also allow OOmode in rs6000_hard_regno_mode_ok so those pair pseudos can be register-allocated, and guard the xxmfacc emission in the DISASSEMBLE_ACC GIMPLE fold with !TARGET_DMF since DMRs are a separate register file and xxmfacc is a no-op. Diff: --- gcc/config/rs6000/mma.md | 14 +++++++------- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 41dd32ca4edd..5f15e3b2e8f6 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -298,7 +298,7 @@ (match_operand:OO 1 "input_operand"))] "" { - if (TARGET_MMA) + if (TARGET_MMA || TARGET_DMF) { rs6000_emit_move (operands[0], operands[1], OOmode); DONE; @@ -323,7 +323,7 @@ (define_insn_and_split "*movoo" [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa") (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))] - "TARGET_MMA + "(TARGET_MMA || TARGET_DMF) && (gpc_reg_operand (operands[0], OOmode) || gpc_reg_operand (operands[1], OOmode))" "@ @@ -391,7 +391,7 @@ [(match_operand:OO 0 "vsx_register_operand") (match_operand:V16QI 1 "mma_assemble_input_operand") (match_operand:V16QI 2 "mma_assemble_input_operand")] - "TARGET_MMA" + "TARGET_MMA || TARGET_DMF" { rtx src = gen_rtx_UNSPEC (OOmode, gen_rtvec (2, operands[1], operands[2]), @@ -408,7 +408,7 @@ (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")] UNSPEC_VSX_ASSEMBLE))] - "TARGET_MMA" + "TARGET_MMA || TARGET_DMF" "#" "&& reload_completed" [(const_int 0)] @@ -424,7 +424,7 @@ [(match_operand:V16QI 0 "mma_disassemble_output_operand") (match_operand:OO 1 "vsx_register_operand") (match_operand 2 "const_0_to_1_operand")] - "TARGET_MMA" + "TARGET_MMA || TARGET_DMF" { rtx src; int regoff = INTVAL (operands[2]); @@ -440,7 +440,7 @@ (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa") (match_operand 2 "const_0_to_1_operand")] UNSPEC_MMA_EXTRACT))] - "TARGET_MMA + "(TARGET_MMA || TARGET_DMF) && vsx_register_operand (operands[1], OOmode)" "#" "&& reload_completed" @@ -482,7 +482,7 @@ (match_operand:V16QI 2 "mma_assemble_input_operand") (match_operand:V16QI 3 "mma_assemble_input_operand") (match_operand:V16QI 4 "mma_assemble_input_operand")] - "TARGET_MMA" + "TARGET_MMA || TARGET_DMF" { if (TARGET_DMF) { diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index db5e3df57ca9..1cf6976cb7b4 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -1180,7 +1180,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, /* If we're disassembling an accumulator into a different type, we need to emit a xxmfacc instruction now, since we cannot do it later. */ - if (fncode == RS6000_BIF_DISASSEMBLE_ACC) + if (fncode == RS6000_BIF_DISASSEMBLE_ACC && !TARGET_DMF) { new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL]; new_call = gimple_build_call (new_decl, 1, src); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 8b479fc29d3e..7017c2d3d43a 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1886,7 +1886,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) /* Vector pair modes need even/odd VSX register pairs. Only allow vector registers. */ if (mode == OOmode) - return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0); + return ((TARGET_MMA || TARGET_DMF) && VSX_REGNO_P (regno) && (regno & 1) == 0); /* MMA accumulator modes need FPR registers divisible by 4. */ if (mode == XOmode)
