https://gcc.gnu.org/g:e225b6ab46dba742b105a9a1648b892e5c336cde
commit r16-9239-ge225b6ab46dba742b105a9a1648b892e5c336cde Author: Stafford Horne <[email protected]> Date: Thu Jun 4 18:36:39 2026 +0100 or1k: Fix 64-bit shifts on OpenRISC On OpenRISC, 64-bit shift tests shiftdi-2.c and vshift-1.c were failing and it looks to always have been broken. After investigation it was found that OpenRISC fails to define SHIFT_COUNT_TRUNCATED which is needed as both register and immediate shift amounts are unsigned and only use the low-order 5 bits. Also, the immediate used for 32-bit shifts is an unsigned 5-bit value not a 6-bit value; update the predicate. After these changes these tests pass. make check-gcc RUNTESTFLAGS='dg.exp=vshift-1.c execute.exp=shiftdi-2.c' gcc/ChangeLog: * config/or1k/or1k.h (SHIFT_COUNT_TRUNCATED): Define. * config/or1k/or1k.md (rotrsi3): Rename reg_or_u6_operand to reg_or_u5_operand. (<shift_op>si3): Ditto. * config/or1k/predicates.md (reg_or_u6_operand): Remove. (reg_or_u5_operand): New predicate. Signed-off-by: Stafford Horne <[email protected]> (cherry picked from commit da222271bcd25927f1641dd6970b4736a42cba43) Diff: --- gcc/config/or1k/or1k.h | 3 +++ gcc/config/or1k/or1k.md | 4 ++-- gcc/config/or1k/predicates.md | 8 ++++---- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h index ee3a7814f09a..af043f8c2d98 100644 --- a/gcc/config/or1k/or1k.h +++ b/gcc/config/or1k/or1k.h @@ -394,6 +394,9 @@ do { \ /* All the work is done in PROFILE_HOOK, but this is still required. */ #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) +/* Shift instructions ignore all but the low-order few bits. */ +#define SHIFT_COUNT_TRUNCATED 1 + /* Dwarf 2 Support */ #define DWARF2_DEBUGGING_INFO 1 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index d3fbb209be70..6de0dc265116 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -217,7 +217,7 @@ (define_insn "<shift_op>si3" [(set (match_operand:SI 0 "register_operand" "=r,r") (SHIFT:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "reg_or_u6_operand" "r,n")))] + (match_operand:SI 2 "reg_or_u5_operand" "r,n")))] "" "@ l.<shift_asm>\t%0, %1, %2 @@ -227,7 +227,7 @@ (define_insn "rotrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (rotatert:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "ror_reg_or_u6_operand" "r,n")))] + (match_operand:SI 2 "ror_reg_or_u5_operand" "r,n")))] "TARGET_ROR || TARGET_RORI" "@ l.ror\t%0, %1, %2 diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index cde49a3754cb..1f78e57366d9 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -38,9 +38,9 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "const0_operand"))) -(define_predicate "reg_or_u6_operand" +(define_predicate "reg_or_u5_operand" (if_then_else (match_code "const_int") - (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x1f") (match_operand 0 "register_operand"))) (define_predicate "reg_or_u16_operand" @@ -53,9 +53,9 @@ (match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767") (match_operand 0 "register_operand"))) -(define_predicate "ror_reg_or_u6_operand" +(define_predicate "ror_reg_or_u5_operand" (if_then_else (match_code "const_int") - (and (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f") + (and (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x1f") (match_test "TARGET_RORI")) (and (match_operand 0 "register_operand") (match_test "TARGET_ROR"))))
