[gcc r17-2196] [PATCH v5] RISC-V: Add small loop unrolling support via -munroll-only-small-loops

Jeff Law via Gcc-cvs Tue, 07 Jul 2026 07:17:52 -0700

https://gcc.gnu.org/g:d15703b27aa4924ca3438066ae0759e7379b3e0b


commit r17-2196-gd15703b27aa4924ca3438066ae0759e7379b3e0b
Author: wangjue <[email protected]>
Date:   Tue Jul 7 08:16:16 2026 -0600

    [PATCH v5] RISC-V: Add small loop unrolling support via 
-munroll-only-small-loops
    
    This patch introduces a conservative loop unrolling heuristic for the
    RISC-V backend, controlled by the new -munroll-only-small-loops option.
    
    When -munroll-only-small-loops is active, only small loops (those whose
    body does not exceed a per-tune instruction threshold) are unrolled, and
    the unroll factor is capped by a per-tune parameter, so that tight loops
    benefit from unrolling without exposing larger loops to its code-size and
    instruction-cache costs.
    
    Mirroring the i386 model, -funroll-loops and -munroll-only-small-loops are
    enabled by default at -O2 and above (for speed).  An explicit -funroll-loops
    (or -funroll-all-loops) turns -munroll-only-small-loops off, so a user who
    explicitly asks for unrolling still gets loops of any size unrolled.  The
    size threshold and the maximum unroll factor come from the -mtune tuning
    parameters.
    
    Since -funroll-loops is now enabled by default at -O2 and above, a number
    of pre-existing RISC-V tests that scan for a specific code sequence change
    their output once loops are unrolled.  As those tests do not aim to exercise
    unrolling, add -fno-unroll-loops to their options so they keep validating
    their intended property regardless of the unrolling decision.
    
    gcc/ChangeLog:
    
            * common/config/riscv/riscv-common.cc 
(riscv_option_optimization_table):
            Enable -funroll-loops and -munroll-only-small-loops at -O2 and 
above.
            * config/riscv/riscv.cc (struct riscv_tune_param): Add fields
            small_loop_unroll_ninsns and small_loop_unroll_factor.
            (xt_c9501_tune_info): Set them.
            (riscv_loop_unroll_adjust): New function.
            (riscv_option_override): Turn off -munroll-only-small-loops when
            -funroll-loops or -funroll-all-loops is explicitly given.
            (TARGET_LOOP_UNROLL_ADJUST): Define.
            * config/riscv/riscv.opt (munroll-only-small-loops): New option.
            * config/riscv/riscv.opt.urls: Regenerate.
            * doc/invoke.texi (RISC-V Options): Document 
-munroll-only-small-loops.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/unroll-explicit.c: New test.
            * gcc.target/riscv/unroll-large-loop.c: New test.
            * gcc.target/riscv/unroll-pragma.c: New test.
            * gcc.target/riscv/unroll-small-loop-tune.c: New test.
            * gcc.target/riscv/unroll-small-loop.c: New test.
            * g++.dg/tree-prof/pr57451.C: Add -fno-unroll-loops.
            * g++.target/riscv/pr97682.C: Likewise.
            * gcc.dg/tree-ssa/pr117973-1.c: Likewise.
            * gcc.dg/vect/vect-alias-check-4.c: Likewise.
            * gcc.target/riscv/pr67731.c: Likewise.
            * gcc.target/riscv/rvv/autovec/pr113206-1.c: Likewise.
            * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Likewise.
            * gcc.target/riscv/rvv/base/pr114352-3.c: Likewise.
            * gcc.target/riscv/rvv/base/scalar_move-7.c: Likewise.
            * gcc.target/riscv/rvv/base/spill-10.c: Likewise.
            * gcc.target/riscv/rvv/base/spill-11.c: Likewise.
            * gcc.target/riscv/rvv/base/spill-12.c: Likewise.
            * gcc.target/riscv/rvv/base/spill-8.c: Likewise.
            * gcc.target/riscv/rvv/base/spill-9.c: Likewise.
            * gcc.target/riscv/rvv/base/vwaddsub-1.c: Likewise.
            * gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: Likewise.
            * gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Likewise.
            * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Likewise.
            * gcc.target/riscv/slt-1.c: Likewise.
            * gcc.target/riscv/struct_vect_24.c: Likewise.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc            |  4 +++
 gcc/config/riscv/riscv.cc                          | 32 ++++++++++++++++++++++
 gcc/config/riscv/riscv.opt                         |  4 +++
 gcc/config/riscv/riscv.opt.urls                    |  3 ++
 gcc/doc/invoke.texi                                | 15 ++++++++++
 gcc/testsuite/g++.dg/tree-prof/pr57451.C           |  1 +
 gcc/testsuite/g++.target/riscv/pr97682.C           |  2 +-
 gcc/testsuite/gcc.dg/tree-ssa/pr117973-1.c         |  1 +
 gcc/testsuite/gcc.dg/vect/vect-alias-check-4.c     |  1 +
 gcc/testsuite/gcc.target/riscv/pr67731.c           |  4 +--
 .../gcc.target/riscv/rvv/autovec/pr113206-1.c      |  2 +-
 .../riscv/rvv/autovec/unop/math-nearbyint-0.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-1.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-2.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-3.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-4.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-5.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-6.c   |  2 +-
 .../riscv/rvv/autovec/vls/calling-convention-7.c   |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-39.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-41.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-45.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-46.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-48.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-49.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-50.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-52.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-56.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-59.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-60.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-61.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-62.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-64.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-65.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-66.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-67.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-68.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-69.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-70.c    |  2 +-
 .../riscv/rvv/base/float-point-dynamic-frm-71.c    |  2 +-
 .../riscv/rvv/base/float-point-frm-insert-4.c      |  2 +-
 .../riscv/rvv/base/float-point-frm-insert-5.c      |  2 +-
 .../gcc.target/riscv/rvv/base/pr114352-3.c         |  2 +-
 .../gcc.target/riscv/rvv/base/scalar_move-7.c      |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c  |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c  |  2 +-
 .../gcc.target/riscv/rvv/base/vwaddsub-1.c         |  2 +-
 .../riscv/rvv/base/zvbb_vandn_vx_constraint.c      |  2 +-
 .../riscv/rvv/base/zvbc_vx_constraint-2.c          |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-4.c     |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-6.c     |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-66.c    |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-1.c        |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-2.c        |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-3.c        |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-4.c        |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-5.c        |  2 +-
 .../riscv/rvv/vsetvl/imm_loop_invariant-6.c        |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-1.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-10.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-14.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-15.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-16.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-17.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-18.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-19.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-20.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-21.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-22.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-23.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-25.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-27.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-3.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-30.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-31.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-35.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-37.c          |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-7.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-8.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-9.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_conflict-11.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c       |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c       |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c       |  2 +-
 gcc/testsuite/gcc.target/riscv/slt-1.c             |  2 +-
 gcc/testsuite/gcc.target/riscv/struct_vect_24.c    |  2 +-
 gcc/testsuite/gcc.target/riscv/unroll-explicit.c   | 22 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/unroll-large-loop.c | 22 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/unroll-pragma.c     | 23 ++++++++++++++++
 .../gcc.target/riscv/unroll-small-loop-tune.c      | 22 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/unroll-small-loop.c | 19 +++++++++++++
 106 files changed, 263 insertions(+), 94 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0ecfd814eba9..783692076a75 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -2351,6 +2351,10 @@ static const struct default_options 
riscv_option_optimization_table[] =
     /* Enable -fsched-pressure starting at -O1.  */
     { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
     { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
+    /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
+       loop unrolling at -O2 and above.  */
+    { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
+    { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
 #if TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1
     { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1},
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 251da7c09998..a8b3bef6c2b7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -300,6 +300,8 @@ struct riscv_tune_param
   const char *jump_align;
   const char *loop_align;
   bool prefer_agnostic;
+  unsigned int small_loop_unroll_ninsns = 4;
+  unsigned int small_loop_unroll_factor = 2;
 };
 
 
@@ -734,6 +736,8 @@ static const struct riscv_tune_param xt_c9501_tune_info = {
   "8",                                         /* jump_align */
   "16",                                                /* loop_align */
   true,                                                /* prefer-agnostic.  */
+  4,   /* small_loop_unroll_ninsns.  */
+  8,   /* small_loop_unroll_factor.  */
 };
 
 /* Costs to use when optimizing for Tenstorrent Ascalon 8 wide.  */
@@ -5080,6 +5084,22 @@ riscv_insn_cost (rtx_insn *insn, bool speed)
   return cost;
 }
 
+/* This function adjusts the unroll factor based on
+   the current tune parameters.  */
+
+static unsigned
+riscv_loop_unroll_adjust (unsigned nunroll, class loop *loop)
+{
+  if (riscv_unroll_only_small_loops && !loop->unroll)
+    {
+      if (loop->ninsns <= tune_param->small_loop_unroll_ninsns)
+       return MIN (tune_param->small_loop_unroll_factor, nunroll);
+      else
+       return 1;
+    }
+  return nunroll;
+}
+
 /* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST.  Like the default implementation,
    but we consider cost units of branch instructions equal to cost units of
    other instructions.  */
@@ -12164,6 +12184,16 @@ riscv_option_override (void)
 
   flag_pcc_struct_return = 0;
 
+  /* Explicit -funroll-loops or -funroll-all-loops turns
+     -munroll-only-small-loops off, allowing the unroller to handle
+     all loops without the conservative small-loop restriction.  */
+  if ((OPTION_SET_P (flag_unroll_loops) && flag_unroll_loops)
+      || (OPTION_SET_P (flag_unroll_all_loops) && flag_unroll_all_loops))
+    {
+      if (!OPTION_SET_P (riscv_unroll_only_small_loops))
+       riscv_unroll_only_small_loops = 0;
+    }
+
   if (flag_pic)
     g_switch_value = 0;
 
@@ -16575,6 +16605,8 @@ riscv_memtag_tag_bitsize ()
 #define TARGET_RTX_COSTS riscv_rtx_costs
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST riscv_address_cost
+#undef TARGET_LOOP_UNROLL_ADJUST
+#define TARGET_LOOP_UNROLL_ADJUST riscv_loop_unroll_adjust
 #undef TARGET_INSN_COST
 #define TARGET_INSN_COST riscv_insn_cost
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index c2670ad87b20..3226367bf8a9 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -454,3 +454,7 @@ Enum(arcv_mpy_option) String(10c) Value(ARCV_MPY_OPTION_10C)
 mmpy-option=
 Target RejectNegative Joined Enum(arcv_mpy_option) Var(arcv_mpy_option) 
Init(ARCV_MPY_OPTION_2C)
 The type of MPY unit used by the RMX-100 core (to be used in combination with 
-mtune=arc-v-rmx-100-series) (default: 2c).
+
+munroll-only-small-loops
+Target Var(riscv_unroll_only_small_loops) Init(0) Save
+Enable conservative small loop unrolling.
diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls
index a11299b310af..15c1a8badc7c 100644
--- a/gcc/config/riscv/riscv.opt.urls
+++ b/gcc/config/riscv/riscv.opt.urls
@@ -129,3 +129,6 @@ UrlSuffix(gcc/RISC-V-Options.html#index-mautovec-segment)
 
 ; skipping UrlSuffix for 'mmpy-option=' due to finding no URLs
 
+munroll-only-small-loops
+UrlSuffix(gcc/RISC-V-Options.html#index-munroll-only-small-loops)
+
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 455ea08d7c73..535ad6ba3ffe 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1349,6 +1349,7 @@ See RS/6000 and PowerPC Options.
 -mno-inline-atomics  -mno-inline-strlen
 -mno-inline-strcmp  -mno-inline-strncmp
 -mstringop-strategy=@var{strategy}
+-munroll-only-small-loops  -mno-unroll-only-small-loops
 -mtls-dialect=desc  -mtls-dialect=trad
 -mrvv-vector-bits=@var{value}  -mrvv-max-lmul=@var{value}
 -madjust-lmul-cost  -mmax-vectorization  -mno-autovec-segment}
@@ -31565,6 +31566,20 @@ of TLS variables.
 Use traditional TLS as the thread-local storage mechanism for dynamic accesses
 of TLS variables.  This is the default.
 
+@opindex munroll-only-small-loops
+@opindex mno-unroll-only-small-loops
+@item -munroll-only-small-loops
+@itemx -mno-unroll-only-small-loops
+Controls conservative small loop unrolling.  It is enabled by default at
+@option{-O2} and above.  When enabled, only loops whose RTL instruction
+count does not exceed a tune-specific threshold are unrolled, and the
+unroll factor is capped by a tune-specific parameter.  This gives better
+utilization of the instruction decoding pipeline without enlarging bigger
+loops.  You can disable it with @option{-mno-unroll-only-small-loops}; it
+is also turned off when @option{-funroll-loops} or
+@option{-funroll-all-loops} is explicitly enabled, so that an explicit
+unrolling request applies to loops of any size.
+
 @opindex mrvv-vector-bits
 @item -mrvv-vector-bits=@var{value}
 Specify how the number of bits for an RVV vector register, as taken from
diff --git a/gcc/testsuite/g++.dg/tree-prof/pr57451.C 
b/gcc/testsuite/g++.dg/tree-prof/pr57451.C
index 8fbc1214095b..44a1dc263935 100644
--- a/gcc/testsuite/g++.dg/tree-prof/pr57451.C
+++ b/gcc/testsuite/g++.dg/tree-prof/pr57451.C
@@ -1,6 +1,7 @@
 // Explicit { dg-require-effective-target exceptions_enabled } so that 
dependent tests don't turn UNRESOLVED for '-fno-exceptions'.
 // { dg-require-effective-target freorder }
 // { dg-options "-O2 -freorder-blocks-and-partition -g" }
+/* { dg-additional-options "-fno-unroll-loops" { target riscv*-*-* } } */
 
 extern "C" void abort (void);
 struct MyException {};
diff --git a/gcc/testsuite/g++.target/riscv/pr97682.C 
b/gcc/testsuite/g++.target/riscv/pr97682.C
index 03c7a447de59..68e332a9993d 100644
--- a/gcc/testsuite/g++.target/riscv/pr97682.C
+++ b/gcc/testsuite/g++.target/riscv/pr97682.C
@@ -1,6 +1,6 @@
 /* PR target/97682 */
 /* { dg-do compile } */
-/* { dg-options "-fPIC -O2 -march=rv64g -mabi=lp64" } */
+/* { dg-options "-fPIC -O2 -march=rv64g -mabi=lp64 -fno-unroll-loops" } */
 
 template <typename ab, int ac> struct g { ab b[ac]; };
 long i, m;
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr117973-1.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr117973-1.c
index 6523b3ce59fe..aa4708ae6702 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr117973-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr117973-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fdump-tree-optimized --param 
logical-op-non-short-circuit=0" } */
+/* { dg-additional-options "-fno-unroll-loops" { target riscv*-*-* } } */
 /* PR tree-optimization/117973 */
 #include "pr111456-1.c"
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-alias-check-4.c 
b/gcc/testsuite/gcc.dg/vect/vect-alias-check-4.c
index 750193e3cd43..136b04ef1a75 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-alias-check-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-alias-check-4.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target vect_int } */
 /* { dg-additional-options "--param vect-max-version-for-alias-checks=0 
-fopt-info-vec-all" } */
+/* { dg-additional-options "-fno-unroll-loops" { target riscv*-*-* } } */
 
 #define N 16
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c 
b/gcc/testsuite/gcc.target/riscv/pr67731.c
index 4e6f609e24df..e0985aac1f46 100644
--- a/gcc/testsuite/gcc.target/riscv/pr67731.c
+++ b/gcc/testsuite/gcc.target/riscv/pr67731.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d" { target { rv64 } } } */
-/* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32" { target { rv32 } } } */
+/* { dg-options "-O2 -march=rv64gcbv -mabi=lp64d -fno-unroll-loops" { target { 
rv64 } } } */
+/* { dg-options "-O2 -march=rv32gcbv -mabi=ilp32 -fno-unroll-loops" { target { 
rv32 } } } */
 
 typedef struct
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
index 45086182aa89..c8e4400b5556 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8 
-fno-unroll-loops" } */
 
 signed char e;
 short f = 8;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c
index 85d5e0acab2d..1d8dc73e633b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize 
-fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize 
-fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2 
-fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "test-math.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
index 14334ba1a947..9552d09f48d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic 
-fno-unroll-loops" } */
 
 #include <stdint-gcc.h>
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
index b9865948087a..fd297e1a6f0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic 
-fno-unroll-loops" } */
 
 #include <stdint-gcc.h>
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
index 552c48ecc490..1dca3a337a4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic 
-fno-unroll-loops" } */
 
 #include <stdint-gcc.h>
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
index 36d4926e4f88..7fcf21271db1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic 
-fno-unroll-loops" } */
 
 #include <stdint-gcc.h>
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 86c2400ce513..4a1ec041898a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index c489a9ff7966..c2ab5ea9d285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 97a3282a6570..7c9d23e748b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
index a892919feb7c..f0cccf761553 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
index 0d40349fb0f8..b1c7570d0ea1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
index 8b5a779467db..72080058be5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
index 3ba4e1f18642..10f6f1dc6085 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable 
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
 
 #include "def.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
index fe497c757db8..5507706ea7e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
index 4f86fcb938a9..5b2835ddf919 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
index 69ccd4fe04d2..029695a79ea9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
index a11a1b45f509..471f68bba9ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
index 2855d5f45624..3b8fb1582865 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
index 3e8a9808ba7e..b2cbbd7b0f4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
index e8fc7bbd6c28..f8d7c77497ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
index 9828987d7d26..1579392fa187 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
index aa9c06f625cc..7cef51d93299 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
index 8a752697cd84..f22e389f05b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
index 96f009185cc0..4a89eb0ff01a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
index 5028b789192a..995400ed2a83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
index 44bf9ffd0593..3dac687db137 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
index 45c8b8408de6..0f2bbf0b1f7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
index 329f98c5c1a9..8efc2d468814 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
index b9240f24ec75..064c93369af8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
index 2008cc60b461..9bc910f2daad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
index cad2f1d5f9c6..30371f600cf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
index a971103c3ee2..ef1bdfc45d78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
index b1c51924567e..6f3cd43dd03a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
index c3170556d2f9..bb054f9b9962 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
index 17e47eb0f414..2398d26b4774 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
index 32c938db123f..ee097dc6be98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
index 4f375e526be9..f3dfb33df7b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O3 -fno-schedule-insns 
-fno-schedule-insns2 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
index cf53aca5c629..4897a22e4721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns 
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns 
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d5a839a2ce9e..67954af0fd50 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 
-fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 
-fno-schedule-insns -fno-schedule-insns2 -O3 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index cbfe92105147..5fd4b30f53de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 
-msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 
-msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -fno-unroll-loops" 
} */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
index 7e83cb7b7c1c..65566d6b09e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -msave-restore -fno-schedule-insns 
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -msave-restore -fno-schedule-insns 
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
index ddc36e888eb4..a3e7c9898e8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns 
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns 
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 void f2 (char*);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 375d3166a468..c0c424c64ae2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns 
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns 
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
index bd3b16829a64..af5cfadf6c32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */
 /* { dg-add-options riscv_v } */
-/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns 
-fno-schedule-insns2 -Wno-pedantic" } */
+/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns 
-fno-schedule-insns2 -Wno-pedantic -fno-unroll-loops" } */
 
 #include <stdint.h>
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
index 0d626095544a..e70b1e326bcd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3 -fno-unroll-loops" 
} */
 #include "riscv_vector.h"
 
 vuint64m1_t test_vandn_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
index 3fb14660af8d..daec087be730 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3 -fno-unroll-loops" } */
 #include "riscv_vector.h"
 
 vuint64m1_t test_vclmul_vx_u64m1_extend(vuint64m1_t vs2, uint32_t rs1, size_t 
vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
index 2ec94b2e4827..9954e3538ab5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
index 5f2ef672c903..26884589a4e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
index cf2ece80beff..aef7377e5228 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
index b6776cd9713e..ef179d09018c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index c174845f7bc6..38ed49455e7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" 
} */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
index cee9e36ff2d3..ad968b03abc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
index 46b79ce23134..19abe42d5bd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
index 05604f83974f..19d79637665e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
index b55f74a323c9..b2a85af55c4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
index 50874c9acb6d..eb2eb78a8747 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
index 63039357fe87..20d7aafa2326 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
index bfa81ba8294e..f79bb848e0d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
index 4ba81601c294..f2f445db290a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
index e10f12ea2059..ad8696903441 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
index 54074836e1d1..662289275a68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
index e2963ddac150..fc1bf6ed894e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
index aa18c3a6180c..9c7940c02449 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
index 81eba9ea2597..1bdb2d2851a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
index a7c1478b2a80..ed7adb82c207 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
index aa18c3a6180c..9c7940c02449 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
index 5f770ae0257c..38a6e3cfc665 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
index dc012c8c1d2d..b6251e7aca7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
index 18700d518e9b..40dfa3f973d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
index c2284c822361..74e10cdd0a01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
index ffa95f90e498..a9f1a8d7a10d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index d997762f8775..1fce7ebc46ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
 // PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index 2b3722decd85..76867b451250 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
 // PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
index af46a81de6fa..ac13999dd0dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
index 4c977e4e169d..10eb6af82147 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
index 2e2fc0282c9a..1724c5ebc32a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
index 4de390c249c5..6ae36ba8793c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
index 945beed5ebb3..b864d6f0dd90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
index 8e613899509c..a82e90d33e56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
index 15e82e08d89f..f26ed8f97d7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
index d1a6a944f40c..752c12c5fdbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index 321eb3b9f298..ee37b53507dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index 29dcfefbd0cf..4aa06ca09dd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 8b6299e99d1f..f13f02f47646 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index 3b836f927d20..a6ffa12a6817 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
index ddc3f2c22a6b..49f28eb846c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-tree-vectorize -fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
index a48bce08596c..7aca370e47f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
index bdea9a23b9e2..c483ced626a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
index 449e46c49f8b..15d498337f90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 
-fno-unroll-loops" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/slt-1.c 
b/gcc/testsuite/gcc.target/riscv/slt-1.c
index 5711757e706d..1504b6113019 100644
--- a/gcc/testsuite/gcc.target/riscv/slt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/slt-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -mbranch-cost=4" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mbranch-cost=4 -fno-unroll-loops" 
} */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
 
 #include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/riscv/struct_vect_24.c 
b/gcc/testsuite/gcc.target/riscv/struct_vect_24.c
index 7c0852f1a552..fbfb9c05a54f 100644
--- a/gcc/testsuite/gcc.target/riscv/struct_vect_24.c
+++ b/gcc/testsuite/gcc.target/riscv/struct_vect_24.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target supports_stack_clash_protection } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -fstack-clash-protection 
-fno-stack-protector" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -fstack-clash-protection 
-fno-stack-protector -fno-unroll-loops" } */
 /* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-Os" "-Oz" 
"-funroll-loops"} } */
 
 #include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-explicit.c 
b/gcc/testsuite/gcc.target/riscv/unroll-explicit.c
new file mode 100644
index 000000000000..bf43fbe9ed2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-explicit.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-funroll-loops -fdump-rtl-loop2_unroll-details 
-fno-tree-vectorize" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } { "" } } */
+
+/* An explicit -funroll-loops turns off the default -munroll-only-small-loops,
+   so a loop exceeding the small-loop instruction threshold is unrolled
+   normally.  */
+
+void
+large_loop_explicit (int *a, int *b, int *c, int *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    {
+      a[i] = b[i] + c[i];
+      d[i] = a[i] * b[i] - c[i];
+      b[i] = c[i] + d[i] + a[i];
+      c[i] = a[i] - d[i] + b[i];
+    }
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c 
b/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
new file mode 100644
index 000000000000..cf3b22479f17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details -fno-tree-vectorize" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops" 
} { "" } } */
+
+/* With the default -O2 small loop unrolling (-munroll-only-small-loops),
+   a loop whose body exceeds the small-loop instruction threshold is NOT
+   unrolled.  */
+
+void
+large_loop (int *a, int *b, int *c, int *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    {
+      a[i] = b[i] + c[i];
+      d[i] = a[i] * b[i] - c[i];
+      b[i] = c[i] + d[i] + a[i];
+      c[i] = a[i] - d[i] + b[i];
+    }
+}
+
+/* { dg-final { scan-rtl-dump-not "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-pragma.c 
b/gcc/testsuite/gcc.target/riscv/unroll-pragma.c
new file mode 100644
index 000000000000..28de8dc55967
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-pragma.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details -fno-tree-vectorize" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops" 
} { "" } } */
+
+/* An explicit "#pragma GCC unroll" sets loop->unroll, which makes
+   riscv_loop_unroll_adjust bypass the -munroll-only-small-loops
+   restriction.  Hence a loop exceeding the small-loop instruction
+   threshold is still unrolled as requested.  */
+
+void
+large_loop_pragma (int *a, int *b, int *c, int *d, int n)
+{
+#pragma GCC unroll 2
+  for (int i = 0; i < n; i++)
+    {
+      a[i] = b[i] + c[i];
+      d[i] = a[i] * b[i] - c[i];
+      b[i] = c[i] + d[i] + a[i];
+      c[i] = a[i] - d[i] + b[i];
+    }
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c 
b/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
new file mode 100644
index 000000000000..2f0c5b95be34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=xt-c9501fdvt -fdump-rtl-loop2_unroll-details 
-fno-tree-vectorize" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops" 
} { "" } } */
+
+/* The xt-c9501fdvt tune model sets small_loop_unroll_factor to 8, so a small
+   loop is unrolled by a factor of 8 (rather than the generic default of 2).
+   The unroller reports the number of extra copies, i.e. factor - 1, so an
+   8x unroll is dumped as "Unrolled loop 7 times".  This verifies the tune
+   parameter actually takes effect; with the default factor the dump would
+   instead read "Unrolled loop 1 times".  */
+
+int
+small_loop (int n)
+{
+  int sum = 0;
+  do
+    sum += n;
+  while (--n);
+  return sum;
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop 7 times" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c 
b/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
new file mode 100644
index 000000000000..3f2ecae2b248
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details -fno-tree-vectorize" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops" 
} { "" } } */
+
+/* Small loop unrolling is enabled by default at -O2 (-funroll-loops with
+   -munroll-only-small-loops), so a loop whose body is within the small-loop
+   instruction threshold is unrolled without any explicit option.  */
+
+int
+small_loop (int n)
+{
+  int sum = 0;
+  do
+    sum += n;
+  while (--n);
+  return sum;
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */

[gcc r17-2196] [PATCH v5] RISC-V: Add small loop unrolling support via -munroll-only-small-loops

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