https://gcc.gnu.org/g:3983a83e5da175b0be41d97fb8b1c22318a657f5
commit 3983a83e5da175b0be41d97fb8b1c22318a657f5 Author: Michael Meissner <[email protected]> Date: Thu Jun 25 15:35:03 2026 -0400 PR target/117251: Improve vector fusion #3 See the following post for a complete explanation of what the patches for PR target/117251: * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html This is patch #2 of 45 to generate the 'XXEVAL' instruction on power10 and power11 instead of using the Altivec 'VANDC' instruction feeding into 'VAND'. The 'XXEVAL' instruction can use all 64 vector registers, instead of the 32 registers that traditional Altivec vector instructions use. By allowing all of the vector registers to be used, it reduces the amount of spilling that a large benchmark generated. For vectors such as: vector int a, b, c, d; This patch will generate a call to xxeval if any of the registers are allocated to traditional floating point registers: Code: Old: New: ===== ==== ==== a = ~ ((~ (c & d)) | b); vnan xxeval a,b,c,d,16d t,c,d vnor a,t,b a = (c & d) ^ b; vand t,c,d xxeval a,b,c,d,30 vxor a,t,b a = (c & d) | b; vand t,c,d xxeval a,b,c,d,31 vor a,t,b a = (c & ~ d) ^ b; vandc t,c,d xxeval a,b,c,d,45 vxor a,t,b a = (c & ~ d) | b; vandc t,c,d xxeval a,b,c,d,47 vor a,t,b a = ~ ((c | ~ d) | b); vorc t,c,d xxeval a,b,c,d,64 vnor a,t,b a = ~ ((c | ~ d) ^ b); vorc t,c,d xxeval a,b,c,d,75 veqv a,t,b a = (c | ~ d) | ~ b; vorc t,c,d xxeval a,b,c,d,79 vorc a,t,b Since fusion using 2 Altivec instructions is slightly faster than using the 'XXEVAL' instruction we prefer to generate the Altivec instructions if we can. In addition, because 'XXEVAL' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2026-06-25 Michael Meissner <[email protected]> gcc/ PR target/117251 * config/rs6000/fusion.md: Regenerate. * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to generate vector/vector fusion if XXEVAL is supported. Diff: --- gcc/config/rs6000/genfusion.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index bdbe798de055..3fc14e6d5eb7 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -259,7 +259,7 @@ sub gen_logical_addsubf "vxor_vnand" => 249, "vandc_vnand" => 253, "vand_vnand" => 254, -y ); + ); KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals;
