https://gcc.gnu.org/g:6467b2d95727a5897b3de376698b50c06ddcb33f
commit 6467b2d95727a5897b3de376698b50c06ddcb33f Author: Michael Meissner <[email protected]> Date: Thu Jun 25 15:06:27 2026 -0400 Revert changes Diff: --- gcc/config/rs6000/constraints.md | 10 - gcc/config/rs6000/fusion.md | 660 ++++++--------- gcc/config/rs6000/genfusion.pl | 101 +-- gcc/config/rs6000/predicates.md | 91 +- gcc/config/rs6000/rs6000.cc | 21 +- gcc/config/rs6000/rs6000.h | 14 - gcc/config/rs6000/rs6000.md | 139 +-- gcc/doc/md.texi | 6 - .../gcc.target/powerpc/p10-vector-fused-1.c | 409 --------- .../gcc.target/powerpc/p10-vector-fused-2.c | 936 --------------------- gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 - 11 files changed, 305 insertions(+), 2106 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 4250cf4e1490..0688655e46e7 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -222,16 +222,6 @@ "An IEEE 128-bit constant that can be loaded into VSX registers." (match_operand 0 "easy_vector_constant_ieee128")) -(define_constraint "eU" - "@internal integer constant that can be loaded with paddis" - (and (match_code "const_int") - (match_operand 0 "paddis_operand"))) - -(define_constraint "eV" - "@A signed integer constant that paddis and paddi instructions generate." - (and (match_code "const_int") - (match_operand 0 "paddis_paddi_operand"))) - ;; A negative 0 constant (define_constraint "eZ" "A floating point -0.0 constant." diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index e1d90583f7b3..416017149d6f 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -1871,170 +1871,146 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,1 vand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand (define_insn "*fuse_vandc_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,2 vandc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vand (define_insn "*fuse_veqv_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,9 veqv %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vand (define_insn "*fuse_vnand_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,14 vnand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vand (define_insn "*fuse_vnor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,8 vnor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vand (define_insn "*fuse_vor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,7 vor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vand (define_insn "*fuse_vorc_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,11 vorc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vand (define_insn "*fuse_vxor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,6 vxor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vandc @@ -2057,23 +2033,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,13 vandc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vandc @@ -2204,23 +2177,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,210 vandc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> veqv @@ -2297,23 +2267,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,75 vorc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> veqv @@ -2336,506 +2303,434 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnand (define_insn "*fuse_vand_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,254 vand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,253 vandc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,246 veqv %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,241 vnand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,247 vnor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnand (define_insn "*fuse_vor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,248 vor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,244 vorc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,249 vxor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnor (define_insn "*fuse_vand_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,224 vand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,208 vandc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,96 veqv %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,16 vnand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,112 vnor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnor (define_insn "*fuse_vor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,128 vor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,64 vorc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,144 vxor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vor (define_insn "*fuse_vand_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,31 vand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vor (define_insn "*fuse_vandc_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,47 vandc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vor (define_insn "*fuse_veqv_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,159 veqv %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vor (define_insn "*fuse_vnand_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,239 vnand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vor (define_insn "*fuse_vnor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,143 vnor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vor (define_insn "*fuse_vor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,127 vor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vor (define_insn "*fuse_vorc_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,191 vorc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vor (define_insn "*fuse_vxor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,111 vxor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vorc @@ -2948,23 +2843,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,79 vorc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vorc @@ -2987,170 +2879,146 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vxor (define_insn "*fuse_vand_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,30 vand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,45 vandc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,150 veqv %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,225 vnand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,135 vnor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vxor (define_insn "*fuse_vor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,120 vor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,180 vorc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,105 vxor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) + (set_attr "length" "8")]) ;; add-add fusion pattern generated by gen_addadd (define_insn "*fuse_add_add" diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 3856296e88ec..04e6ab15da6e 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -211,76 +211,25 @@ sub gen_logical_addsubf $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name, - $fuse_type, $xxeval, $c5, $vect_pred, $vect_inner_arg0, $vect_inner_arg1, - $vect_inner_exp, $vect_outer_arg2, $vect_outer_exp); - - my %xxeval_fusions = ( - "vand_vand" => 1, - "vandc_vand" => 2, - "vxor_vand" => 6, - "vor_vand" => 7, - "vnor_vand" => 8, - "veqv_vand" => 9, - "vorc_vand" => 11, - "vandc_vandc" => 13, - "vnand_vand" => 14, - "vnand_vnor" => 16, - "vand_vxor" => 30, - "vand_vor" => 31, - "vandc_vxor" => 45, - "vandc_vor" => 47, - "vorc_vnor" => 64, - "vorc_veqv" => 75, - "vorc_vorc" => 79, - "veqv_vnor" => 96, - "vxor_vxor" => 105, - "vxor_vor" => 111, - "vnor_vnor" => 112, - "vor_vxor" => 120, - "vor_vor" => 127, - "vor_vnor" => 128, - "vnor_vxor" => 135, - "vnor_vor" => 143, - "vxor_vnor" => 144, - "veqv_vxor" => 150, - "veqv_vor" => 159, - "vorc_vxor" => 180, - "vorc_vor" => 191, - "vandc_vnor" => 208, - "vandc_veqv" => 210, - "vand_vnor" => 224, - "vnand_vxor" => 225, - "vnand_vor" => 239, - "vnand_vnand" => 241, - "vorc_vnand" => 244, - "veqv_vnand" => 246, - "vnor_vnand" => 247, - "vor_vnand" => 248, - "vxor_vnand" => 249, - "vandc_vnand" => 253, - "vand_vnand" => 254, - ); - - KIND: foreach $kind ('scalar','vector') { + $fuse_type); + KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; $mode = "VM"; $pred = "altivec_register_operand"; - $vect_pred = "vector_fusion_operand"; $constraint = "v"; $fuse_type = "fused_vector"; } else { $vchr = ""; $mode = "GPR"; - $vect_pred = $pred = "gpc_reg_operand"; + $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; push (@outer_ops, @addsub); push (@outer_ops, ( "rsubf" )); } $c4 = "${constraint},${constraint},${constraint},${constraint}"; - $c5 = "${constraint},${constraint},${constraint},wa,${constraint}"; OUTER: foreach $outer ( @outer_ops ) { $outer_name = "${vchr}${outer}"; $is_subf = ( $outer eq "subf" ); @@ -314,33 +263,23 @@ sub gen_logical_addsubf $bc = ""; if ( $both_commute ) { $bc = "%"; } $inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")"; $inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")"; - $vect_inner_arg0 = "(match_operand:${mode} 0 \"${vect_pred}\" \"${c5}\")"; - $vect_inner_arg1 = "(match_operand:${mode} 1 \"${vect_pred}\" \"${bc}${c5}\")"; if ( ($inner_comp & 1) == 1 ) { $inner_arg0 = "(not:${mode} $inner_arg0)"; - $vect_inner_arg0 = "(not:${mode} $vect_inner_arg0)"; } if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; - $vect_inner_arg1 = "(not:${mode} $vect_inner_arg1)"; } $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; - $vect_inner_exp = "(${inner_rtl}:${mode} ${vect_inner_arg0} - ${vect_inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; - $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } $outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")"; - $vect_outer_arg2 = "(match_operand:${mode} 2 \"${vect_pred}\" \"${c5}\")"; if ( ($outer_comp & 1) == 1 ) { $outer_arg2 = "(not:${mode} $outer_arg2)"; - $vect_outer_arg2 = "(not:${mode} $vect_outer_arg2)"; } if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; - $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } if ( $is_subf ) { $outer_32 = "%2,%3"; @@ -352,23 +291,15 @@ sub gen_logical_addsubf if ( $is_rsubf == 1 ) { $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2} ${inner_exp})"; - $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_outer_arg2} - ${vect_inner_exp})"; } else { $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; - $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_inner_exp} - ${vect_outer_arg2})"; } if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; - $vect_outer_exp = "(not:${mode} $vect_outer_exp)"; } - # See if we can use xxeval on vector fusion - $xxeval = $xxeval_fusions{"${inner_op}_${outer_name}"}; - if (!$xxeval) { - $insn = <<"EOF"; + $insn = <<"EOF"; ;; $ftype fusion pattern generated by gen_logical_addsubf ;; $kind $inner_op -> $outer_name @@ -387,30 +318,6 @@ sub gen_logical_addsubf (set_attr "length" "8")]) EOF - } else { - $insn = <<"EOF"; - -;; $ftype fusion pattern generated by gen_logical_addsubf -;; $kind $inner_op -> $outer_name -(define_insn "*fuse_${inner_op}_${outer_name}" - [(set (match_operand:${mode} 3 "${vect_pred}" "=&0,&1,&${constraint},wa,${constraint}") - ${vect_outer_exp}) - (clobber (match_scratch:${mode} 4 "=X,X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION)" - "@ - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - xxeval %x3,%x2,%x1,%x0,${xxeval} - ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}" - [(set_attr "type" "$fuse_type") - (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,xxeval,*")]) -EOF - } - print $insn; } } diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 841619570c11..073524bedc83 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -119,18 +119,6 @@ return VSX_REGNO_P (REGNO (op)); }) -;; Return 1 if op is a register that can be used for vector fusion. If XXEVAL -;; is supported, return true for all VSX registers, otherwise the fusion is -;; limited to Altivec registers since the machine only fuses Altivec -;; operations. -(define_predicate "vector_fusion_operand" - (match_operand 0 "register_operand") -{ - return (TARGET_XXEVAL - ? vsx_register_operand (op, mode) - : altivec_register_operand (op, mode)); -}) - ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" @@ -390,68 +378,6 @@ return SIGNED_INTEGER_34BIT_P (INTVAL (op)); }) -;; Return 1 if op is a 64-bit constant that uses the paddis instruction -(define_predicate "paddis_operand" - (match_code "const_int") -{ - if (!TARGET_PADDIS) - return false; - - if (mode != VOIDmode && mode != DImode) - return false; - - HOST_WIDE_INT value = INTVAL (op); - - if (!SIGNED_INTEGER_64BIT_P (value)) - return false; - - /* If paddi alone can handle the number, don't return true. */ - if (SIGNED_INTEGER_34BIT_P (value)) - return false; - - /* If the bottom 32-bits are non-zero, paddis alone can't handle it. */ - if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0) - return false; - - return true; -}) - -;; Return 1 if op is a 64-bit constant that can be created with a -;; combination of paddi and paddis. Don't generate paddi and paddis if -;; we can do it via addis and rldicl. -(define_predicate "paddis_paddi_operand" - (match_code "const_int") -{ - if (!TARGET_PADDIS) - return false; - - if (mode != VOIDmode && mode != DImode) - return false; - - HOST_WIDE_INT value = INTVAL (op); - - if (!SIGNED_INTEGER_64BIT_P (value)) - return false; - - /* Don't worry about negative values at the moment. */ - if (value < 0) - return false; - - /* If paddi alone can handle the number, don't return true. */ - if (SIGNED_INTEGER_34BIT_P (value)) - return false; - - /* If we can do the add or generate the constant via addis/rldicl, fail. */ - if (rs6000_is_valid_and_mask (op, mode)) - return false; - - /* Only return true if we need both paddi and paddis. */ - if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0) - return false; - - return true; -}) - ;; Return 1 if op is a register that is not special. ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where ;; you need to be careful in moving a SFmode to SImode and vice versa due to @@ -642,22 +568,18 @@ (ior (match_operand 0 "zero_constant") (match_operand 0 "gpc_reg_operand"))) -;; Return 1 if op is a constant integer valid for addition with addis, -;; addi, paddi, or paddis. +;; Return 1 if op is a constant integer valid for addition with addis, addi. (define_predicate "add_cint_operand" (and (match_code "const_int") - (ior (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) - + (mode == SImode ? 0x80000000 : 0x80008000)) - < (unsigned HOST_WIDE_INT) 0x100000000ll") - (match_operand 0 "cint34_operand") - (match_operand 0 "paddis_operand")))) + (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) + + (mode == SImode ? 0x80000000 : 0x80008000)) + < (unsigned HOST_WIDE_INT) 0x100000000ll"))) ;; Return 1 if op is a constant integer valid for addition ;; or non-special register. (define_predicate "reg_or_add_cint_operand" (if_then_else (match_code "const_int") - (ior (match_operand 0 "add_cint_operand") - (match_operand 0 "paddis_paddi_operand")) + (match_operand 0 "add_cint_operand") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if op is a constant integer valid for subtraction @@ -1209,8 +1131,7 @@ (if_then_else (match_code "const_int") (match_test "satisfies_constraint_I (op) || satisfies_constraint_L (op) - || satisfies_constraint_eI (op) - || satisfies_constraint_eU (op)") + || satisfies_constraint_eI (op)") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if the operand is either a non-special register, or 0, or -1. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e228c636ef7b..dff53bef1a24 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6245,18 +6245,7 @@ num_insns_constant_gpr (HOST_WIDE_INT value) else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value)) return 1; - /* PADDIS support. */ - else if (TARGET_PADDIS) - { - rtx num = GEN_INT (value); - if (paddis_operand (num, VOIDmode)) - return 1; /* paddis alone. */ - - if (paddis_paddi_operand (num, VOIDmode)) - return 2; /* paddis + paddi/addi. */ - } - - if (TARGET_POWERPC64) + else if (TARGET_POWERPC64) { int num_insns = 0; rs6000_emit_set_long_const (nullptr, value, &num_insns); @@ -14484,14 +14473,6 @@ print_operand (FILE *file, rtx x, int code) fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4); return; - case 'B': - /* Upper 32-bits of a constant. */ - if (!CONST_INT_P (x)) - output_operand_lossage ("Not a constant."); - - fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32); - return; - case 'D': /* Like 'J' but get to the GT bit only. */ if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 96a34f9aa3be..6ad50ee5764c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -526,10 +526,6 @@ extern int rs6000_vector_align[]; #define TARGET_MMA_DENSE_MATH (TARGET_MMA && TARGET_DENSE_MATH) #define TARGET_MMA_NO_DENSE_MATH (TARGET_MMA && !TARGET_DENSE_MATH) -/* Enable XXEVAL support if we support prefixed instructions and at least - power10. */ -#define TARGET_XXEVAL (TARGET_POWER10 && TARGET_PREFIXED) - /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx> options that have not yet been replaced by their OPTION_MASK_<xxx> @@ -598,9 +594,6 @@ extern int rs6000_vector_align[]; /* Whether we have XVRLW support. */ #define TARGET_XVRLW TARGET_FUTURE -/* Whether we have PADDIS support. */ -#define TARGET_PADDIS (TARGET_FUTURE && TARGET_POWERPC64) - /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction by default. */ @@ -2526,13 +2519,6 @@ typedef struct GTY(()) machine_function #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) -#if HOST_BITS_PER_WIDE_INT > 64 -#define SIGNED_INTEGER_64BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 64) - -#else -#define SIGNED_INTEGER_64BIT_P(VALUE) 1 -#endif - /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra argument that gives a length to validate a range of addresses, to allow for splitting insns into several insns, each of which has an offsettable diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ea18c1ad301b..19eff4ac497f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -372,7 +372,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,future,paddis,xxeval" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,future" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -428,15 +428,6 @@ (and (eq_attr "isa" "future") (match_test "TARGET_FUTURE")) (const_int 1) - - (and (eq_attr "isa" "paddis") - (match_test "TARGET_PADDIS")) - (const_int 1) - - (and (eq_attr "isa" "xxeval") - (match_test "TARGET_XXEVAL")) - (const_int 1) - ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor @@ -1918,18 +1909,14 @@ (match_operand:SDI 2 "reg_or_add_cint_operand")))] "" { - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - if (<MODE>mode == DImode && !TARGET_POWERPC64) { - rtx lo0 = gen_lowpart (SImode, op0); - rtx lo1 = gen_lowpart (SImode, op1); - rtx lo2 = gen_lowpart (SImode, op2); - rtx hi0 = gen_highpart (SImode, op0); - rtx hi1 = gen_highpart (SImode, op1); - rtx hi2 = gen_highpart_mode (SImode, DImode, op2); + rtx lo0 = gen_lowpart (SImode, operands[0]); + rtx lo1 = gen_lowpart (SImode, operands[1]); + rtx lo2 = gen_lowpart (SImode, operands[2]); + rtx hi0 = gen_highpart (SImode, operands[0]); + rtx hi1 = gen_highpart (SImode, operands[1]); + rtx hi2 = gen_highpart_mode (SImode, DImode, operands[2]); if (!reg_or_short_operand (lo2, SImode)) lo2 = force_reg (SImode, lo2); @@ -1941,40 +1928,24 @@ DONE; } - if (CONST_INT_P (op2) && !add_operand (op2, <MODE>mode)) + if (CONST_INT_P (operands[2]) && !add_operand (operands[2], <MODE>mode)) { - rtx tmp = ((!can_create_pseudo_p () || rtx_equal_p (op0, op1)) - ? op0 - : gen_reg_rtx (<MODE>mode)); + rtx tmp = ((!can_create_pseudo_p () + || rtx_equal_p (operands[0], operands[1])) + ? operands[0] : gen_reg_rtx (<MODE>mode)); /* Adding a constant to r0 is not a valid insn, so use a different strategy in that case. */ - if (reg_or_subregno (op1) == 0 || reg_or_subregno (tmp) == 0) + if (reg_or_subregno (operands[1]) == 0 || reg_or_subregno (tmp) == 0) { - if (op0 == op1) + if (operands[0] == operands[1]) FAIL; - rs6000_emit_move (op0, op2, <MODE>mode); - emit_insn (gen_add<mode>3 (op0, op1, op0)); - DONE; - } - - HOST_WIDE_INT val = INTVAL (op2); - - /* If we have paddis, split the add into paddis and either addi or - paddi. However, if we can generate addis and rldicl, do that - instead of doing paddis/paddi. Emit the paddis first, just - in case this is a memory operation and we could fold the offset - into the memory ooperation. */ - - if (TARGET_PADDIS && paddis_paddi_operand (op2, <MODE>mode)) - { - const HOST_WIDE_INT mask = HOST_WIDE_INT_C(0xffffffff); - - emit_insn (gen_add<mode>3 (tmp, op1, GEN_INT (val & ~mask))); - emit_insn (gen_add<mode>3 (op0, tmp, GEN_INT (val & mask))); + rs6000_emit_move (operands[0], operands[2], <MODE>mode); + emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[0])); DONE; } + HOST_WIDE_INT val = INTVAL (operands[2]); HOST_WIDE_INT low = sext_hwi (val, 16); HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); @@ -1984,28 +1955,24 @@ /* The ordering here is important for the prolog expander. When space is allocated from the stack, adding 'low' first may produce a temporary deallocation (which would be bad). */ - emit_insn (gen_add<mode>3 (tmp, op1, GEN_INT (rest))); - emit_insn (gen_add<mode>3 (op0, tmp, GEN_INT (low))); + emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); + emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); DONE; } }) (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r, r, r") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b, b, b") - (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b") + (match_operand:GPR 2 "add_operand" "r,I,L,eI")))] "" "@ add %0,%1,%2 addi %0,%1,%2 addis %0,%1,%v2 - addi %0,%1,%2 - paddis %0,%1,%B2" + addi %0,%1,%2" [(set_attr "type" "add") - (set_attr "isa" "*,*,*,p10,paddis") - (set_attr "length" "*,*,*,*,12") - (set_attr "prefixed" "*,*,*,*,yes") - (set_attr "maybe_prefixed" "*,*,*,*,no")]) + (set_attr "isa" "*,*,*,p10")]) (define_insn "*addsi3_high" [(set (match_operand:SI 0 "gpc_reg_operand" "=b") @@ -10028,7 +9995,7 @@ DONE; }) -;; GPR store GPR load GPR move GPR paddis GPR paddis+paddi +;; GPR store GPR load GPR move ;; GPR li GPR lis GPR pli GPR # ;; FPR store FPR load FPR move ;; AVX store AVX store AVX load AVX load VSX move @@ -10038,7 +10005,7 @@ ;; VSX->GPR GPR->VSX (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=YZ, r, r, r, b, + "=YZ, r, r, r, r, r, r, m, ^d, ^d, wY, Z, $v, $v, ^wa, @@ -10047,7 +10014,7 @@ r, *h, *h, ?r, ?wa") (match_operand:DI 1 "input_operand" - "r, YZ, r, eU, eV, + "r, YZ, r, I, L, eI, nF, ^d, m, ^d, ^v, $v, wY, Z, ^wa, @@ -10062,8 +10029,6 @@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 mr %0,%1 - paddis %0,0,%B1 - # li %0,%1 lis %0,%v1 li %0,%1 @@ -10089,7 +10054,7 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, *, *, + "store, load, *, *, *, *, *, fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, @@ -10099,7 +10064,7 @@ mfvsr, mtvsr") (set_attr "size" "64") (set_attr "length" - "*, *, *, 12, 24, + "*, *, *, *, *, *, 20, *, *, *, *, *, *, *, *, @@ -10108,32 +10073,14 @@ *, *, *, *, *") (set_attr "isa" - "*, *, *, paddis, paddis, + "*, *, *, *, *, p10, *, *, *, *, p9v, p7v, p9v, p7v, *, p9v, p9v, p7v, *, *, p7v, p7v, *, *, *, - p8v, p8v") - (set_attr "prefixed" - "*, *, *, yes, yes, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, - *, *, *, - *, *") - (set_attr "maybe_prefixed" - "*, *, *, no, no, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, - *, *, *, - *, *")]) + p8v, p8v")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. @@ -10151,32 +10098,6 @@ (match_dup 1)))] "") -;; Split a constant that can be generated by a paddis and paddi into 2 -;; instructions. We can't split setting r0 since that would generate: -;; paddis r0,0,upper -;; paddi r0,r0,lower -;; -;; which gives the wrong value. - -(define_split - [(set (match_operand:DI 0 "base_reg_operand") - (match_operand:DI 1 "paddis_paddi_operand"))] - "TARGET_PADDIS" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (plus:DI (match_dup 2) - (match_dup 4)))] -{ - HOST_WIDE_INT value = INTVAL (operands[1]); - const HOST_WIDE_INT mask = HOST_WIDE_INT_C (0xffffffff); - operands[2] = (can_create_pseudo_p () - ? gen_reg_rtx (DImode) - : operands[0]); - operands[3] = GEN_INT (value & ~mask); - operands[4] = GEN_INT (value & mask); -}) - ;; Split a load of a large constant into the appropriate five-instruction ;; sequence. Handle anything in a constant number of insns. ;; When non-easy constants can go in the TOC, this should use diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index b22d9092ea2d..f227353bd82c 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3368,12 +3368,6 @@ loaded to a VSX register with one prefixed instruction. An IEEE 128-bit constant that can be loaded into a VSX register with the @code{lxvkq} instruction. -@item eU -A signed integer constant that can be used with the paddis instruction. - -@item eV -A signed integer constant that paddis and paddi instructions generate. - @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c b/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c deleted file mode 100644 index 28e0874b3454..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c +++ /dev/null @@ -1,409 +0,0 @@ -/* { dg-do run } */ -/* { dg-require-effective-target power10_hw } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Generate and check most of the vector logical instruction combinations that - may or may not generate xxeval to do a fused operation on power10. */ - -#include <stddef.h> -#include <stdlib.h> -#include <altivec.h> - -#ifdef DEBUG -#include <stdio.h> - -static int errors = 0; -static int tests = 0; -#endif - -typedef vector unsigned int vector_t; -typedef unsigned int scalar_t; - -/* Vector logical functions. */ -static inline vector_t -vector_and (vector_t x, vector_t y) -{ - return x & y; -} - -static inline vector_t -vector_or (vector_t x, vector_t y) -{ - return x | y; -} - -static inline vector_t -vector_xor (vector_t x, vector_t y) -{ - return x ^ y; -} - -static inline vector_t -vector_andc (vector_t x, vector_t y) -{ - return x & ~y; -} - -static inline vector_t -vector_orc (vector_t x, vector_t y) -{ - return x | ~y; -} - -static inline vector_t -vector_nand (vector_t x, vector_t y) -{ - return ~(x & y); -} - -static inline vector_t -vector_nor (vector_t x, vector_t y) -{ - return ~(x | y); -} - -static inline vector_t -vector_eqv (vector_t x, vector_t y) -{ - return ~(x ^ y); -} - -/* Scalar logical functions. */ -static inline scalar_t -scalar_and (scalar_t x, scalar_t y) -{ - return x & y; -} - -static inline scalar_t -scalar_or (scalar_t x, scalar_t y) -{ - return x | y; -} - -static inline scalar_t -scalar_xor (scalar_t x, scalar_t y) -{ - return x ^ y; -} - -static inline scalar_t -scalar_andc (scalar_t x, scalar_t y) -{ - return x & ~y; -} - -static inline scalar_t -scalar_orc (scalar_t x, scalar_t y) -{ - return x | ~y; -} - -static inline scalar_t -scalar_nand (scalar_t x, scalar_t y) -{ - return ~(x & y); -} - -static inline scalar_t -scalar_nor (scalar_t x, scalar_t y) -{ - return ~(x | y); -} - -static inline scalar_t -scalar_eqv (scalar_t x, scalar_t y) -{ - return ~(x ^ y); -} - - -/* - * Generate one function for each combination that we are checking. Do 4 - * operations: - * - * Use FPR regs that should generate either XXEVAL or XXL* insns; - * Use Altivec registers than may generated fused V* insns; - * Use VSX registers, insure fusing it not done via asm; (and) - * Use GPR registers on scalar operations. - */ - -#ifdef DEBUG -#define TRACE(INNER, OUTER) \ - do { \ - tests++; \ - printf ("%s_%s\n", INNER, OUTER); \ - fflush (stdout); \ - } while (0) \ - -#define FAILED(INNER, OUTER) \ - do { \ - errors++; \ - printf ("%s_%s failed\n", INNER, OUTER); \ - fflush (stdout); \ - } while (0) \ - -#else -#define TRACE(INNER, OUTER) -#define FAILED(INNER, OUTER) abort () -#endif - -#define FUSED_FUNC(INNER, OUTER) \ -static void \ -INNER ## _ ## OUTER (vector_t a, vector_t b, vector_t c) \ -{ \ - vector_t f_a, f_b, f_c, f_r, f_t; \ - vector_t v_a, v_b, v_c, v_r, v_t; \ - vector_t w_a, w_b, w_c, w_r, w_t; \ - scalar_t s_a, s_b, s_c, s_r, s_t; \ - \ - TRACE (#INNER, #OUTER); \ - \ - f_a = a; \ - f_b = b; \ - f_c = c; \ - \ - __asm__ (" # fpr regs: %x0,%x1,%x2 " #INNER "_" #OUTER \ - : "+d" (f_a), \ - "+d" (f_b), \ - "+d" (f_c)); \ - \ - f_t = vector_ ## INNER (f_b, f_c); \ - f_r = vector_ ## OUTER (f_a, f_t); \ - \ - __asm__ (" # fpr regs result: %x0 " #INNER "_" #OUTER \ - : "+d" (f_r)); \ - \ - v_a = a; \ - v_b = b; \ - v_c = c; \ - \ - __asm__ (" # altivec regs: %x0,%x1,%x2 " #INNER "_" #OUTER \ - : "+v" (v_a), \ - "+v" (v_b), \ - "+v" (v_c)); \ - \ - v_t = vector_ ## INNER (v_b, v_c); \ - v_r = vector_ ## OUTER (v_a, v_t); \ - \ - __asm__ (" # altivec regs result: %x0 " #INNER "_" #OUTER \ - : "+v" (v_r)); \ - \ - w_a = a; \ - w_b = b; \ - w_c = c; \ - \ - __asm__ (" # vsx regs: %x0,%x1,%x2 " #INNER "_" #OUTER \ - : "+wa" (w_a), \ - "+wa" (w_b), \ - "+wa" (w_c)); \ - \ - w_t = vector_ ## INNER (w_b, w_c); \ - __asm__ ("nop # break vsx fusion reg %x0" : "+wa" (w_t)); \ - w_r = vector_ ## OUTER (w_a, w_t); \ - \ - __asm__ (" # vsx regs result: %x0 " #INNER "_" #OUTER \ - : "+wa" (w_r)); \ - \ - s_a = a[0]; \ - s_b = b[0]; \ - s_c = c[0]; \ - \ - __asm__ (" # gpr regs: %0,%1,%2 " #INNER "_" #OUTER \ - : "+r" (s_a), \ - "+r" (s_b), \ - "+r" (s_c)); \ - \ - s_t = scalar_ ## INNER (s_b, s_c); \ - s_r = scalar_ ## OUTER (s_a, s_t); \ - \ - __asm__ (" # gpr regs result: %0 " #INNER "_" #OUTER \ - : "+r" (s_r)); \ - \ - if (!vec_all_eq (w_r, f_r) \ - || !vec_all_eq (w_r, v_r) \ - || s_r != w_r[0]) \ - FAILED (#INNER, #OUTER); \ - \ - return; \ -} - -FUSED_FUNC (and, and) -FUSED_FUNC (andc, and) -FUSED_FUNC (eqv, and) -FUSED_FUNC (nand, and) -FUSED_FUNC (nor, and) -FUSED_FUNC (or, and) -FUSED_FUNC (orc, and) -FUSED_FUNC (xor, and) - -FUSED_FUNC (and, andc) -FUSED_FUNC (andc, andc) -FUSED_FUNC (eqv, andc) -FUSED_FUNC (nand, andc) -FUSED_FUNC (nor, andc) -FUSED_FUNC (or, andc) -FUSED_FUNC (orc, andc) -FUSED_FUNC (xor, andc) - -FUSED_FUNC (and, eqv) -FUSED_FUNC (andc, eqv) -FUSED_FUNC (eqv, eqv) -FUSED_FUNC (nand, eqv) -FUSED_FUNC (nor, eqv) -FUSED_FUNC (or, eqv) -FUSED_FUNC (orc, eqv) -FUSED_FUNC (xor, eqv) - -FUSED_FUNC (and, nand) -FUSED_FUNC (andc, nand) -FUSED_FUNC (eqv, nand) -FUSED_FUNC (nand, nand) -FUSED_FUNC (nor, nand) -FUSED_FUNC (or, nand) -FUSED_FUNC (orc, nand) -FUSED_FUNC (xor, nand) - -FUSED_FUNC (and, nor) -FUSED_FUNC (andc, nor) -FUSED_FUNC (eqv, nor) -FUSED_FUNC (nand, nor) -FUSED_FUNC (nor, nor) -FUSED_FUNC (or, nor) -FUSED_FUNC (orc, nor) -FUSED_FUNC (xor, nor) - -FUSED_FUNC (and, or) -FUSED_FUNC (andc, or) -FUSED_FUNC (eqv, or) -FUSED_FUNC (nand, or) -FUSED_FUNC (nor, or) -FUSED_FUNC (or, or) -FUSED_FUNC (orc, or) -FUSED_FUNC (xor, or) - -FUSED_FUNC (and, orc) -FUSED_FUNC (andc, orc) -FUSED_FUNC (eqv, orc) -FUSED_FUNC (nand, orc) -FUSED_FUNC (nor, orc) -FUSED_FUNC (or, orc) -FUSED_FUNC (orc, orc) -FUSED_FUNC (xor, orc) - -FUSED_FUNC (and, xor) -FUSED_FUNC (andc, xor) -FUSED_FUNC (eqv, xor) -FUSED_FUNC (nand, xor) -FUSED_FUNC (nor, xor) -FUSED_FUNC (or, xor) -FUSED_FUNC (orc, xor) -FUSED_FUNC (xor, xor) - - -/* List of functions to check. */ -typedef void func_t (vector_t, - vector_t, - vector_t); - -typedef func_t *ptr_func_t; - -static ptr_func_t functions[] = { - and_and, - andc_and, - eqv_and, - nand_and, - nor_and, - or_and, - orc_and, - xor_and, - - and_andc, - andc_andc, - eqv_andc, - nand_andc, - nor_andc, - or_andc, - orc_andc, - xor_andc, - - and_eqv, - andc_eqv, - eqv_eqv, - nand_eqv, - nor_eqv, - or_eqv, - orc_eqv, - xor_eqv, - - and_nand, - andc_nand, - eqv_nand, - nand_nand, - nor_nand, - or_nand, - orc_nand, - xor_nand, - - and_nor, - andc_nor, - eqv_nor, - nand_nor, - nor_nor, - or_nor, - orc_nor, - xor_nor, - - and_or, - andc_or, - eqv_or, - nand_or, - nor_or, - or_or, - orc_or, - xor_or, - - and_orc, - andc_orc, - eqv_orc, - nand_orc, - nor_orc, - or_orc, - orc_orc, - xor_orc, - - and_xor, - andc_xor, - eqv_xor, - nand_xor, - nor_xor, - or_xor, - orc_xor, - xor_xor, -}; - - -int -main (void) -{ - scalar_t s_a = 0x0fu; - scalar_t s_b = 0xaau; - scalar_t s_c = 0xccu; - - vector_t a = (vector_t) { s_a, s_a, ~s_a, ~s_a }; - vector_t b = (vector_t) { s_b, ~s_b, s_b, ~s_b }; - vector_t c = (vector_t) { s_c, ~s_c, ~s_c, s_c }; - - size_t i; - - for (i = 0; i < sizeof (functions) / sizeof (functions[0]); i++) - functions[i] (a, b, c); - -#ifdef DEBUG - printf ("Done, %d tests, %d failures\n", tests, errors); - return errors; - -#else - return 0; -#endif -} diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c b/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c deleted file mode 100644 index f074622c9f67..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c +++ /dev/null @@ -1,936 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Make sure all of the fusion cases that generate the xxeval instruction - actually generate it. */ -typedef vector unsigned int vector_t; - -static inline vector_t -vector_and (vector_t x, vector_t y) -{ - return x & y; -} - -static inline vector_t -vector_or (vector_t x, vector_t y) -{ - return x | y; -} - -static inline vector_t -vector_xor (vector_t x, vector_t y) -{ - return x ^ y; -} - -static inline vector_t -vector_andc (vector_t x, vector_t y) -{ - return x & ~y; -} - -static inline vector_t -vector_orc (vector_t x, vector_t y) -{ - return x | ~y; -} - -static inline vector_t -vector_nand (vector_t x, vector_t y) -{ - return ~(x & y); -} - -static inline vector_t -vector_nor (vector_t x, vector_t y) -{ - return ~(x | y); -} - -static inline vector_t -vector_eqv (vector_t x, vector_t y) -{ - return ~(x ^ y); -} - -void -and_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,1. */ - r = vector_and (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -and_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,14. */ - r = vector_andc (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -and_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,31. */ - r = vector_or (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -and_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,239. */ - r = vector_orc (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -and_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,30. */ - r = vector_xor (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,14. */ - r = vector_andc (a, vector_and (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,11. */ - r = vector_andc (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,210. */ - r = vector_eqv (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,239. */ - r = vector_nand (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,47. */ - r = vector_or (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,191. */ - r = vector_orc (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -andc_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,45. */ - r = vector_xor (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -eqv_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,9. */ - r = vector_and (a, vector_eqv (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -eqv_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,210. */ - r = vector_eqv (a, vector_andc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -eqv_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,105. */ - r = vector_eqv (a, vector_eqv (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -eqv_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,159. */ - r = vector_or (a, vector_eqv (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -eqv_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,111. */ - r = vector_orc (a, vector_eqv (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nand_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,14. */ - r = vector_and (a, vector_nand (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nand_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,1. */ - r = vector_andc (a, vector_nand (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nand_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,30. */ - r = vector_eqv (a, vector_nand (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nand_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,2. */ - r = vector_nor (a, vector_nand (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nand_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,31. */ - r = vector_orc (a, vector_nand (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,8. */ - r = vector_and (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,7. */ - r = vector_andc (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,120. */ - r = vector_eqv (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,191. */ - r = vector_nand (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,143. */ - r = vector_or (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -nor_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,127. */ - r = vector_orc (a, vector_nor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -or_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,7. */ - r = vector_and (a, vector_or (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -or_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,8. */ - r = vector_andc (a, vector_or (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -or_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,127. */ - r = vector_or (a, vector_or (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -or_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,143. */ - r = vector_orc (a, vector_or (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -or_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,120. */ - r = vector_xor (a, vector_or (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,11. */ - r = vector_and (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,2. */ - r = vector_andc (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,75. */ - r = vector_eqv (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_nor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,8. */ - r = vector_nor (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,191. */ - r = vector_or (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,47. */ - r = vector_orc (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -orc_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,180. */ - r = vector_xor (a, vector_orc (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,6. */ - r = vector_and (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,9. */ - r = vector_andc (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,249. */ - r = vector_nand (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,111. */ - r = vector_or (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,159. */ - r = vector_orc (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -void -xor_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r) -{ - vector_t a = *p_a; - vector_t b = *p_b; - vector_t c = *p_c; - vector_t r; - - __asm__ (" # force fpr registers, %x0,%x1,%x2" - : "+d" (a), "+d" (b), "+d" (c)); - - /* xxeval r,a,b,c,105. */ - r = vector_xor (a, vector_xor (b, c)); - - __asm__ (" # force fpr result, %x0" : "+d" (r)); - *p_r = r; - return; -} - -/* Make sure none of traditional logical instructions are generated. Skip - checking for xxlor in case the register allocator decides to add some vector - moves. */ -/* { dg-final { scan-assembler-not {\mv(and|or|xor|andc|orc|nand|nor|eqv)\M} } } */ -/* { dg-final { scan-assembler-not {\mxxl(and|xor|andc|orc|nand|nor|eqv)\M} } } */ -/* { dg-final { scan-assembler-times {\mxxeval\M} 46 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c deleted file mode 100644 index d08e3675f94c..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c +++ /dev/null @@ -1,24 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_future_ok } */ -/* { dg-require-effective-target lp64 } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test whether the xvrl (vector word rotate left using VSX registers insead of - Altivec registers is generated. */ - -#include <stddef.h> - -size_t -prefix_addis_addi (size_t x) -{ - return x + 0x123456789ABCDEUL; /* paddis + paddi. */ -} - -size_t -prefix_addis (size_t x) -{ - return x + 0x12345600000000UL; /* paddis. */ -} - -/* { dg-final { scan-assembler-times {\mpaddis\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
