https://gcc.gnu.org/g:ffc1b2f3e5d8e63ec810b761778546c6f8704287
commit r17-1708-gffc1b2f3e5d8e63ec810b761778546c6f8704287 Author: Peter Bergner <[email protected]> Date: Thu Jun 18 04:33:03 2026 +0000 riscv: Change tt-ascalon-d8 to tt-ascalon-x The Ascalon cpu's official marketing name is Ascalon X. Change the -mcpu= and -mtune= options to accept tt-ascalon-x as the cpu's canonical name. Create an alias name so the old option names are still accepted. 2026-06-17 Peter Bergner <[email protected]> gcc/ * config/riscv/riscv-cores.def (RISCV_TUNE)<tt-ascalon-d8>: Rename from this... (RISCV_TUNE)<tt-ascalon-x>: ...to this. (RISCV_CORE)<tt-ascalon-d8>: Likewise. (RISCV_CORE)<tt-ascalon-x>: Likewise. (RISCV_CORE_ALIAS): Add tt-ascalon-d8 alias for tt-ascalon-x. * doc/riscv-mcpu.texi: Document the name change. * doc/riscv-mtune.texi: Likewise. Signed-off-by: Peter Bergner <[email protected]> Diff: --- gcc/config/riscv/riscv-cores.def | 7 ++++--- gcc/doc/riscv-mcpu.texi | 2 +- gcc/doc/riscv-mtune.texi | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 9dd355c29a7d..fc92a70bc747 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -40,7 +40,7 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) -RISCV_TUNE("tt-ascalon-d8", tt_ascalon_d8, tt_ascalon_d8_tune_info) +RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("xt-c908", xt_c908, xt_c908_tune_info) RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info) @@ -172,10 +172,11 @@ RISCV_CORE("xt-c9501fdvt", "rva23s64_zfbfmin_zfh_zicfilp_zicfiss_zkr_zmmul_" "svadu_svvptc", "xt-c9501fdvt") -RISCV_CORE("tt-ascalon-d8", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" +RISCV_CORE("tt-ascalon-x", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" "smstateen_ssaia_ssstrict_svadu", - "tt-ascalon-d8") + "tt-ascalon-x") +RISCV_CORE_ALIAS("tt-ascalon-x", "tt-ascalon-d8") RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi index 0f774c560d6a..2dbb39458093 100644 --- a/gcc/doc/riscv-mcpu.texi +++ b/gcc/doc/riscv-mcpu.texi @@ -62,7 +62,7 @@ by particular CPU name. Permissible values for this option are: @samp{xt-c9501fdvt}, -@samp{tt-ascalon-d8}, +@samp{tt-ascalon-x}, @samp{xiangshan-nanhu}, diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi index 7aef8e63f8cc..681436ff500c 100644 --- a/gcc/doc/riscv-mtune.texi +++ b/gcc/doc/riscv-mtune.texi @@ -30,7 +30,7 @@ particular CPU name. Permissible values for this option are: @samp{sifive-p600-series}, -@samp{tt-ascalon-d8}, +@samp{tt-ascalon-x}, @samp{thead-c906},
