https://gcc.gnu.org/g:029f08d94805ab7a51dcadc12296ad6dd6ec05ef
commit 029f08d94805ab7a51dcadc12296ad6dd6ec05ef Author: Michael Meissner <[email protected]> Date: Thu Jun 18 23:28:34 2026 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.test | 83 +++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 61 insertions(+), 22 deletions(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index 0a60edb44104..6d9bdb820d27 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,8 +1,45 @@ -==================== Branch work247-float, patch #210 ==================== +==================== Branch work247-dmf, patch #120 ==================== + +Add paddis support. + +This patch adds support for the paddis instruction that might be added to a +future PowerPC processor. + +2026-06-09 Michael Meissner <[email protected]> + +gcc/ + + * config/rs6000/constraints.md (eU): New constraint. + (eV): Likewise. + * config/rs6000/predicates.md (paddis_operand): New predicate. + (paddis_paddi_operand): Likewise. + (add_cint_operand): Add paddis support. + (reg_or_add_cint_operand): Add support for adds that can be done with + paddis and paddi/addi. + (add_operand): Add support for adds that can be done with paddis, but + not paddis + paddi/addi.. + * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add support for adds + that can be done with paddis and also paddis combined with paddi/addi. + (print_operand): Add %B<n> for paddis support. + * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. + (SIGNED_INTEGER_64BIT_P): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add paddis support. + (enabled attribute); Likewise. + (add<mode>3 define_expand): Likewise. + (*add<mode>3 define_insn): Likewise. + (movdi_internal64): Add paddis and paddis+paddi support. + (movdi splitter): New splitter for paddis + paddi/addi. + * doc/md.texi (PowerPC constraints): Add eU and eV documentation. + +gcc/testsuite/ + + * gcc.target/powerpc/prefixed-addis.c: New test. + +==================== Branch work247-float, patch #230 ==================== Add _Float16 and __bfloat16 tests. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/testsuite/ @@ -17,11 +54,11 @@ gcc/testsuite/ (check_ppc_bfloat16_runtime_available): Likewise. (is-effective-target): Add new _Float16 and __bfloat16 targets. -==================== Branch work247-float, patch #209 ==================== +==================== Branch work247-float, patch #229 ==================== Add --with-powerpc-float16 and --with-powerpc-float16-disable-warning. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -33,7 +70,7 @@ gcc/ (ISA_2_7_MASKS_SERVER): Likewise. (POWERPC_MASKS): Likewise. -==================== Branch work247-float, patch #208 ==================== +==================== Branch work247-float, patch #228 ==================== Optimize __bfloat16 scalar code. @@ -79,7 +116,7 @@ BFmode because GCC will not generate these patterns unless the user uses -Ofast. Without -Ofast, it will always convert BFmode into SFmode. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -102,11 +139,11 @@ gcc/ * config/rs6000/rs6000-protos.h (bfloat16_operation_as_v4sf): New declaration. -==================== Branch work247-float, patch #200 ==================== +==================== Branch work247-float, patch #227 ==================== Add 16-bit floating point vectorization. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -140,11 +177,11 @@ gcc/ (fp16_vectorization): New declaration. * config/rs6000/t-rs6000 (float16.o): Add build rules. -==================== Branch work247-float, patch #206 ==================== +==================== Branch work247-float, patch #226 ==================== Add BF/HF neg, abs operands and logical insns. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -165,11 +202,11 @@ gcc/ (boolc<mode>3): Likewise. (boolcc<mode>): Likewise. -==================== Branch work247-float, patch #205 ==================== +==================== Branch work247-float, patch #225 ==================== Add conversions between 16-bit floating point and other scalar modes. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -184,7 +221,7 @@ gcc/ (fix_trunc<FP16_HW:mode><GPR:mode>): Likewise. (fixuns_trunc<FP16_HW:mode><GPR:mode>2): Likewise. -==================== Branch work247-float, patch #204 ==================== +==================== Branch work247-float, patch #224 ==================== Add conversions between __bfloat16 and float/double. @@ -223,7 +260,7 @@ float/double value. GCC will generation. xscvdpsp 0,0 Convert float scalar to float memory format xvcvspbf16 0,0 Convert vector float to vector __bfloat16 -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -243,6 +280,8 @@ gcc/ (shift_bf_16bits): Likewise. (trunc<mode>bf): New insns to convert SFmode/DFmode to BFmode. (vsx_xscvdpspn_sf): Likewise. + (trunchfbf2): New insn to convert BFmode to HFmode. + (extendbfhf2): New insn to convert HFmode to BFmode. (cvt_fp16_to_v4sf_<mode): Likewise. (cvt_fp16_to_v4sf_<mode>_le): Likewise. (cvt_fp16_to_v4sf_<mode>_be): Likewise. @@ -255,14 +294,14 @@ gcc/ * config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Mark that we use VSX arithmetic support for V8BFmode if we are a power10 or later. -==================== Branch work247-float, patch #203 ==================== +==================== Branch work247-float, patch #223 ==================== Add conversions between _Float16 and float/double. This patch adds support to generate xscvhpdp and xscvdphp on Power9 systems and later, to convert between _Float16 and float scalar values. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -275,14 +314,14 @@ gcc/ * config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Mark that we use VSX arithmetic support for V8HFmode if we are a power9 or later. -==================== Branch work247-float, patch #202 ==================== +==================== Branch work247-float, patch #222 ==================== Add HF/BF emulation functions to libgcc. This patch adds the necessary support in libgcc to allow using the machine independent 16-bit floating point support. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> libgcc/ @@ -327,7 +366,7 @@ libgcc/ supports _Float16 and __bfloat16 types. * configure: Regenerate. -==================== Branch work247-float, patch #201 ==================== +==================== Branch work247-float, patch #221 ==================== Add initial 16-bit floating point support. @@ -343,7 +382,7 @@ usable, the next patch will also need to be installed. That patch will add support in libgcc for 16-bit floating point support. -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/ @@ -412,7 +451,7 @@ gcc/ * config/rs6000/rs6000.opt (-mloat16): New option. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mfloat16. -==================== Branch work247-float, patch #200 ==================== +==================== Branch work247-float, patch #220 ==================== Add infrastructure for _Float16 and __bfloat16 types. @@ -462,7 +501,7 @@ will be added in the next patch. V4HFmode -- 64-bit vector mode _Float16 used in some insns -2026-06-04 Michael Meissner <[email protected]> +2026-06-18 Michael Meissner <[email protected]> gcc/
