https://gcc.gnu.org/g:d2d9b902132e4ae5298b7a62d82dc4af3dc74a52
commit r16-8458-gd2d9b902132e4ae5298b7a62d82dc4af3dc74a52 Author: Takayuki 'January June' Suwa <[email protected]> Date: Fri Apr 3 10:58:09 2026 +0900 xtensa: Small change to the alternative negsf2 pattern The previously added alternative negsf2 pattern (for cases where both source and destination are GP registers) directly specified multiple machine instructions in the output template, but this patch replaces that with an RTL representation using the split pattern, to increase opportunities for instruction reordering. gcc/ChangeLog: * config/xtensa/xtensa.md (negsf2): Change define_insn to define_insn_and_split, and replace the corresponding output template with the split pattern. Diff: --- gcc/config/xtensa/xtensa.md | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 6916adefc8bd..a96ea6feb60f 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -693,15 +693,25 @@ DONE; }) -(define_insn "negsf2" +(define_insn_and_split "negsf2" [(set (match_operand:SF 0 "register_operand") (neg:SF (match_operand:SF 1 "register_operand"))) (clobber (match_scratch:SI 2))] "TARGET_HARD_FLOAT" {@ [cons: =0, 1, =2; attrs: type, length] - [D, D, &a; arith , 7] movi.n\t%2, 1\;slli\t%2, %2, 31\;add.n\t%0, %1, %2 + [D, D, &a; arith , 7] # [f, f, X; farith, 3] neg.s\t%0, %1 } + "&& reload_completed && REG_P (operands[2])" + [(set (match_dup 2) + (const_int 1)) + (set (match_dup 2) + (ashift:SI (match_dup 2) + (const_int 31))) + (set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 1) 0) + (match_dup 2)))] + "" [(set_attr "mode" "SF")])
