https://gcc.gnu.org/g:e984cf7f6519b8d22803caf340c961d2728314bc
commit r16-6509-ge984cf7f6519b8d22803caf340c961d2728314bc Author: Tamar Christina <[email protected]> Date: Mon Jan 5 20:55:05 2026 +0000 vect: update tests for -ftrapping-math support [PR122103] Before going any further, this updates the existing testcases that really require -fno-trapping-math to now use that. It also adds three new tests for SVE. They will however fail until the last patch but that's fine. Notable is testcase gcc.target/aarch64/sve/unpacked_cond_frinta_2.c which without -ftrapping-math (which it's explicitly checking for) generates worse code because the vectorizer forces an unneeded unpack. This is however the same issue with how the vectorizer picks VF as we've seen a number of times. gcc/testsuite/ChangeLog: PR tree-optimization/122103 * gcc.target/aarch64/sve/unpacked_frinta_1.c: Add -fno-trapping-math. * gcc.target/aarch64/sve/unpacked_frinti_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_frintm_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_frintp_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_frintx_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_frintz_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_frinta_2.c: Likewise. * gcc.target/aarch64/sve/vcond_13.c: Likewise. * gcc.target/aarch64/sve/vcond_14.c: Likewise. * gcc.target/aarch64/sve/vcond_15.c: Likewise. * gcc.target/aarch64/sve/vcond_16.c: Likewise. * gcc.target/i386/avx-pr93078.c: Likewise. * gcc.target/i386/avx512f-pr93078.c: Likewise. Diff: --- .../gcc.target/aarch64/sve/unpacked_cond_frinta_2.c | 18 +++++++++++------- .../gcc.target/aarch64/sve/unpacked_frinta_1.c | 6 +++--- .../gcc.target/aarch64/sve/unpacked_frinti_1.c | 6 +++--- .../gcc.target/aarch64/sve/unpacked_frintm_1.c | 6 +++--- .../gcc.target/aarch64/sve/unpacked_frintp_1.c | 6 +++--- .../gcc.target/aarch64/sve/unpacked_frintx_1.c | 6 +++--- .../gcc.target/aarch64/sve/unpacked_frintz_1.c | 6 +++--- gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c | 2 +- gcc/testsuite/gcc.target/i386/avx-pr93078.c | 2 +- gcc/testsuite/gcc.target/i386/avx512f-pr93078.c | 2 +- 13 files changed, 35 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c index f20e2e6d4453..539dffc31752 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c @@ -3,16 +3,20 @@ #include "unpacked_cond_frinta_1.c" -/* Test that we don't drop SELs without -fno-trapping-math. */ +/* Test that operations that can raise FE exceptions are properly masked + even when not using -fno-trapping-math. However when using masking we hit + the existing problem where the vectorizer tries to match VF rather than + number of elements. This means we could have generated better code here + using widening loads, but we can't as the vectorizer forces an unrolling. */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ -/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ -/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 { xfail *-*-* } } } */ /* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ /* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */ +/* { dg-final { scan-assembler-times {\tsel\t} 6 { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c index 3cbdef3d99be..5411089cb72d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_roundf16, _Float16, uint32_t, 64) TEST_FN (__builtin_roundf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c index 7645fed5136a..27401de597f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_nearbyintf16, _Float16, uint32_t, 64) TEST_FN (__builtin_nearbyintf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c index 98f85fb5bfee..69502b071aa1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_floorf16, _Float16, uint32_t, 64) TEST_FN (__builtin_floorf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c index f2336979ad0f..12a7c7eadfce 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_ceilf16, _Float16, uint32_t, 64) TEST_FN (__builtin_ceilf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c index 73403a54ecbb..152bda5cc2ba 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_rintf16, _Float16, uint32_t, 64) TEST_FN (__builtin_rintf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c index 73778431c2ee..f09f19cbc5f2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ #include <stdint.h> @@ -20,8 +20,8 @@ TEST_FN (__builtin_truncf16, _Float16, uint32_t, 64) TEST_FN (__builtin_truncf32, float, uint64_t, 32) -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ -/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 0 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 0 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c index 3c3aa00f6741..701991946cb8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ #define N 119 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c index 1144461dec0e..a5aa85356c68 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ #define N 119 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c index 4967074072c7..f8c5f3058320 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ #define N 119 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c index 7fa98716830b..115c9903511c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ #define N 119 diff --git a/gcc/testsuite/gcc.target/i386/avx-pr93078.c b/gcc/testsuite/gcc.target/i386/avx-pr93078.c index 3fedeaa0c656..e4834918e099 100644 --- a/gcc/testsuite/gcc.target/i386/avx-pr93078.c +++ b/gcc/testsuite/gcc.target/i386/avx-pr93078.c @@ -1,6 +1,6 @@ /* PR target/93078 */ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2 -mprefer-vector-width=256 -masm=att" } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mno-avx2 -mprefer-vector-width=256 -masm=att -fno-trapping-math" } */ /* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$12,\[^\n\r]*%y" } } */ /* { dg-final { scan-assembler "vroundps\[ \t]\+\\\$4,\[^\n\r]*%y" } } */ /* { dg-final { scan-assembler "vroundpd\[ \t]\+\\\$12,\[^\n\r]*%y" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c index 72d6c25bff14..b9e308932d95 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr93078.c @@ -1,6 +1,6 @@ /* PR target/93078 */ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512 -masm=att" } */ +/* { dg-options "-O2 -ftree-vectorize -mavx512f -mprefer-vector-width=512 -masm=att -fno-trapping-math" } */ /* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$12,\[^\n\r]*%z" } } */ /* { dg-final { scan-assembler "vrndscaleps\[ \t]\+\\\$4,\[^\n\r]*%z" } } */ /* { dg-final { scan-assembler "vrndscalepd\[ \t]\+\\\$12,\[^\n\r]*%z" } } */
