https://gcc.gnu.org/g:91ee2e628475f156a57f5c7777a79a77bea86fc6
commit r16-6503-g91ee2e628475f156a57f5c7777a79a77bea86fc6 Author: Pan Li <[email protected]> Date: Mon Jan 5 09:28:04 2026 -0700 [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx mis combine [PR123317] From: Pan Li <[email protected]> Add test cases for the mis combine of the vwadd/vwsub vx combine. PR target/123317 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr123317-run-1.c: New test. * gcc.target/riscv/rvv/autovec/pr123317-run-2.c: New test. * gcc.target/riscv/rvv/autovec/pr123317-run-3.c: New test. * gcc.target/riscv/rvv/autovec/pr123317-run-4.c: New test. * gcc.target/riscv/rvv/autovec/pr123317-run.h: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../gcc.target/riscv/rvv/autovec/pr123317-run-1.c | 8 ++++ .../gcc.target/riscv/rvv/autovec/pr123317-run-2.c | 8 ++++ .../gcc.target/riscv/rvv/autovec/pr123317-run-3.c | 8 ++++ .../gcc.target/riscv/rvv/autovec/pr123317-run-4.c | 8 ++++ .../gcc.target/riscv/rvv/autovec/pr123317-run.h | 49 ++++++++++++++++++++++ 5 files changed, 81 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-1.c new file mode 100644 index 000000000000..9ef18efd0659 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v } */ +/* { dg-additional-options "-std=c99 -Os --param=gpr2vr-cost=0 -Wno-pedantic" } */ + +#define OP -= +#define EXPECT 0x881 + +#include "pr123317-run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-2.c new file mode 100644 index 000000000000..ceab87fb5add --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v } */ +/* { dg-additional-options "-std=c99 -O2 --param=gpr2vr-cost=0 -Wno-pedantic" } */ + +#define OP -= +#define EXPECT 0x881 + +#include "pr123317-run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-3.c new file mode 100644 index 000000000000..8abe890af9e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v } */ +/* { dg-additional-options "-std=c99 -Os --param=gpr2vr-cost=0 -Wno-pedantic" } */ + +#define OP += +#define EXPECT 0x350000000000005c + +#include "pr123317-run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-4.c new file mode 100644 index 000000000000..bdbd12681fca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v } */ +/* { dg-additional-options "-std=c99 -O2 --param=gpr2vr-cost=0 -Wno-pedantic" } */ + +#define OP += +#define EXPECT 0x350000000000005c + +#include "pr123317-run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run.h new file mode 100644 index 000000000000..b5255b26e9ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123317-run.h @@ -0,0 +1,49 @@ +#ifndef HAVE_DEFINED_PR123317_RUN_H +#define HAVE_DEFINED_PR123317_RUN_H + +#include <stdint.h> + +#define BS_VEC(type, num) type __attribute__((vector_size(num * sizeof(type)))) +#define safe_mod_func_uint32_t_u_u(_ui1, _ui2) \ + ({ \ + uint32_t ui1 = _ui1; \ + uint32_t ui2 = _ui2; \ + ui2 == 0 ? ui1 : 0; \ + }) + +uint64_t BS_CHECKSUM; +int32_t g_1577; + +void func_5(int32_t p_8, int32_t p_9, uint64_t p_10) { + BS_VEC(uint64_t, 4) BS_VAR_1[9] = {}; + uint64_t LOCAL_CHECKSUM = 0; + int32_t l_1981 = 0; + + for (p_10 = 0; p_10 <= 4; p_10 += g_1577 -= 1) { + l_1981 ^= safe_mod_func_uint32_t_u_u(p_8, p_9); + BS_VAR_1[0] OP (BS_VEC(uint64_t, 4)){l_1981, l_1981, l_1981, l_1981}; + } + + for (uint32_t BS_TEMP_121 = 0; BS_TEMP_121 < 9; BS_TEMP_121++) + for (uint32_t BS_TEMP_122 = 0; BS_TEMP_122 < 4; BS_TEMP_122++) + LOCAL_CHECKSUM ^= + BS_VAR_1[BS_TEMP_121][BS_TEMP_122] + LOCAL_CHECKSUM >> 2; + + BS_CHECKSUM += LOCAL_CHECKSUM; +} + +void func_1() { + int16_t l_32 = (int16_t)42122; + func_5(l_32, 0, l_32); +} + +int main() { + func_1(); + + if (BS_CHECKSUM != EXPECT) + __builtin_abort(); + + return 0; +} + +#endif
