https://gcc.gnu.org/g:43ec8ef603f5f8c3b75dffc2d50c8112b11f7d77
commit r16-6499-g43ec8ef603f5f8c3b75dffc2d50c8112b11f7d77 Author: Pan Li <[email protected]> Date: Sun Dec 28 16:40:39 2025 +0800 RISC-V: Adjust the asm check of vx_vf due to middle-end change The middle-end adjust the depth_limit, thus adjust the asm check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Adjust the asm check. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 5 ++++- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 5 ++++- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 +- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index 6776b1f24b21..1e2eecf30a98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -36,4 +36,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vmin.vx} } } */ /* { dg-final { scan-assembler-not {vsadd.vx} } } */ /* { dg-final { scan-assembler-not {vssub.vx} } } */ -/* { dg-final { scan-assembler-not {vaadd.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-mrvv-max-lmul=m2" + "-mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c index 3a8e85f6e230..e42fffebea18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -32,6 +32,6 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vremu.vx} } } */ /* { dg-final { scan-assembler {vmaxu.vx} } } */ /* { dg-final { scan-assembler {vminu.vx} } } */ -/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ /* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index 060d591c159f..3703055229d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -34,4 +34,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ -/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts { + "-mrvv-max-lmul=m2" + "-mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c index 79b747704d9e..82467decb97c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -32,6 +32,6 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vremu.vx} } } */ /* { dg-final { scan-assembler {vmaxu.vx} } } */ /* { dg-final { scan-assembler {vminu.vx} } } */ -/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ /* { dg-final { scan-assembler {vaaddu.vx} } } */
