https://gcc.gnu.org/g:d3e111071a0dfa6e953b3827cc4d7d70139737f8
commit d3e111071a0dfa6e953b3827cc4d7d70139737f8 Author: Michael Meissner <[email protected]> Date: Fri Dec 12 10:21:15 2025 -0500 Revert changes Diff: --- gcc/ChangeLog.float | 28 ++-------------------------- gcc/config/rs6000/float16.md | 27 ++++----------------------- gcc/config/rs6000/rs6000.opt | 8 -------- 3 files changed, 6 insertions(+), 57 deletions(-) diff --git a/gcc/ChangeLog.float b/gcc/ChangeLog.float index 56f61b9e265a..a3ba9d5bd814 100644 --- a/gcc/ChangeLog.float +++ b/gcc/ChangeLog.float @@ -1,29 +1,5 @@ -==================== Branch work231-float, patch #221 ==================== - -Add -mbfloat16-combine for testing. - -2025-12-12 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (extendbf<mode>): Disable if - -mbfloat16-combine. - * config/rs6000/rs6000.opt (-mbfloat16-combine): New debug option. - -==================== Branch work231-float, patch #220 ==================== - -Add -mbfloat16-vector for testing. - -2025-12-11 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (xscvspdpn_sf): If -mbfloat16-vector, - generate vector code, not scalar. - (<fp16_vector8>_shift_left_32bit): Likewise. - (<fp16_vector8>_shift_left_32bit_new): Likewise. - (<fp16_vector8>_shift_left_32bit_orig): Likewise. - * config/rs6000/rs6000.opt (-mbfloat16-vector): New debug option. +==================== Branch work231-float, patch #221 was reverted ==================== +==================== Branch work231-float, patch #220 was reverted ==================== ==================== Branch work231-float, patch #210 ==================== diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 685aba48805f..fe5422dc2892 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -234,7 +234,7 @@ (float_extend:SFDF (match_operand:BF 1 "vsx_register_operand" "v"))) (clobber (match_scratch:V8BF 2 "=v"))] - "TARGET_BFLOAT16_HW && !TARGET_BFLOAT16_COMBINE" + "TARGET_BFLOAT16_HW" "#" "&& 1" [(pc)] @@ -281,36 +281,17 @@ (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" -{ - return (TARGET_BFLOAT16_VECTOR - ? "xvcvspdp %x0,%x1" - : "xscvspdpn %x0,%x1"); -} + "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) ;; Vector shift left by 32 bits to get the 16-bit floating point value ;; into the upper 32 bits for the conversion. -(define_expand "<fp16_vector8>_shift_left_32bit" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand") - (unspec:<FP16_VECTOR8> - [(match_operand:FP16_HW 1 "vsx_register_operand")] - UNSPEC_FP16_SHIFT_LEFT_32BIT))]) - -(define_insn "*<fp16_vector8>_shift_left_32bit_new" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=v") - (unspec:<FP16_VECTOR8> - [(match_operand:FP16_HW 1 "vsx_register_operand" "v")] - UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "TARGET_BFLOAT16_VECTOR" - "vspltw %0,%1,1" - [(set_attr "type" "vecperm")]) - -(define_insn "*<fp16_vector8>_shift_left_32bit_orig" +(define_insn "<fp16_vector8>_shift_left_32bit" [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa") (unspec:<FP16_VECTOR8> [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "!TARGET_BFLOAT16_VECTOR" + "" "xxsldwi %x0,%x1,%x1,1" [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 2faba44ed9ee..c0fbe9bb2713 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -643,14 +643,6 @@ mfloat16 Target Mask(FLOAT16) Var(rs6000_isa_flags) Enable or disable 16-bit floating point. -mbfloat16-vector -Target Var(TARGET_BFLOAT16_VECTOR) Init(0) Save Undocumented -Change the code for bfloat16 conversions. - -mbfloat16-combine -Target Var(TARGET_BFLOAT16_COMBINE) Init(0) Save Undocumented -Change the code for bfloat16 conversions #2. - ; Documented parameters -param=rs6000-vect-unroll-limit=
