https://gcc.gnu.org/g:eb5f0c77260dc2b6518f5a3de142400c02dc4ad2
commit r16-5286-geb5f0c77260dc2b6518f5a3de142400c02dc4ad2 Author: Christophe Lyon <[email protected]> Date: Fri Sep 19 13:08:33 2025 +0000 arm: [MVE intrinsics] rework uqrshll uqrshll_sat48 Implement uqrshll and uqrshll_sat48 using the new MVE builtins framework. gcc/ChangeLog: * config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): Add ss_UQRSHLL, ss_UQRSHLL_SAT48. (mve_function_scalar_shift): Add support for ss_UQRSHLL, ss_UQRSHLL_SAT48. * config/arm/arm-mve-builtins-base.def (uqrshll, uqrshll_sat48): New. * config/arm/arm-mve-builtins-base.h (uqrshll, uqrshll_sat48): New. * config/arm/arm_mve.h (uqrshll): Delete. (uqrshll_sat48): Delete. (__arm_uqrshll): Delete. (__arm_uqrshll_sat48): Delete. * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Add '@' prefix. Diff: --- gcc/config/arm/arm-mve-builtins-base.cc | 12 ++++++++++++ gcc/config/arm/arm-mve-builtins-base.def | 2 ++ gcc/config/arm/arm-mve-builtins-base.h | 2 ++ gcc/config/arm/arm_mve.h | 16 ---------------- gcc/config/arm/mve.md | 2 +- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index 60fc2f364d66..3a450f11468d 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -1172,6 +1172,8 @@ public: enum which_scalar_shift { ss_ASRL, ss_LSLL, + ss_UQRSHLL, + ss_UQRSHLL_SAT48, }; class mve_function_scalar_shift : public function_base @@ -1201,6 +1203,14 @@ public: code = CODE_FOR_mve_lsll; break; + case ss_UQRSHLL: + code = code_for_mve_uqrshll_sat_di (UQRSHLL_64); + break; + + case ss_UQRSHLL_SAT48: + code = code_for_mve_uqrshll_sat_di (UQRSHLL_48); + break; + default: gcc_unreachable (); } @@ -1397,6 +1407,8 @@ namespace arm_mve { FUNCTION (asrl, mve_function_scalar_shift, (ss_ASRL)) FUNCTION (lsll, mve_function_scalar_shift, (ss_LSLL)) +FUNCTION (uqrshll, mve_function_scalar_shift, (ss_UQRSHLL)) +FUNCTION (uqrshll_sat48, mve_function_scalar_shift, (ss_UQRSHLL_SAT48)) FUNCTION_PRED_P_S_U (vabavq, VABAVQ) FUNCTION_WITHOUT_N (vabdq, VABDQ) FUNCTION (vabsq, unspec_based_mve_function_exact_insn, (ABS, ABS, ABS, -1, -1, -1, VABSQ_M_S, -1, VABSQ_M_F, -1, -1, -1)) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index 6fb584b3d858..84a77252b855 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -20,6 +20,8 @@ #define REQUIRES_FLOAT false DEF_MVE_FUNCTION (asrl, scalar_s64_shift, none, none) DEF_MVE_FUNCTION (lsll, scalar_u64_shift, none, none) +DEF_MVE_FUNCTION (uqrshll, scalar_u64_shift, none, none) +DEF_MVE_FUNCTION (uqrshll_sat48, scalar_u64_shift, none, none) DEF_MVE_FUNCTION (vabavq, binary_acca_int32, all_integer, p_or_none) DEF_MVE_FUNCTION (vabdq, binary, all_integer, mx_or_none) DEF_MVE_FUNCTION (vabsq, unary, all_signed, mx_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 22dcd93992d8..5b8cb6e95a61 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -25,6 +25,8 @@ namespace functions { extern const function_base *const asrl; extern const function_base *const lsll; +extern const function_base *const uqrshll; +extern const function_base *const uqrshll_sat48; extern const function_base *const vabavq; extern const function_base *const vabdq; extern const function_base *const vabsq; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 32193f6edfdd..2f43fd72a2bb 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -88,8 +88,6 @@ #define srshr(__p0, __p1) __arm_srshr(__p0, __p1) #define srshrl(__p0, __p1) __arm_srshrl(__p0, __p1) #define uqrshl(__p0, __p1) __arm_uqrshl(__p0, __p1) -#define uqrshll(__p0, __p1) __arm_uqrshll(__p0, __p1) -#define uqrshll_sat48(__p0, __p1) __arm_uqrshll_sat48(__p0, __p1) #define uqshl(__p0, __p1) __arm_uqshl(__p0, __p1) #define uqshll(__p0, __p1) __arm_uqshll(__p0, __p1) #define urshr(__p0, __p1) __arm_urshr(__p0, __p1) @@ -244,20 +242,6 @@ __arm_vgetq_lane_u64 (uint64x2_t __a, const int __idx) return __a[__ARM_LANEQ(__a,__idx)]; } -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_uqrshll (uint64_t value, int32_t shift) -{ - return __builtin_mve_uqrshll_sat64_di (value, shift); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_uqrshll_sat48 (uint64_t value, int32_t shift) -{ - return __builtin_mve_uqrshll_sat48_di (value, shift); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_sqrshrl (int64_t value, int32_t shift) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index fd996b2dab06..434194d51113 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -4278,7 +4278,7 @@ ;; ;; [uqrshll_di] ;; -(define_insn "mve_uqrshll_sat<supf>_di" +(define_insn "@mve_uqrshll_sat<supf>_di" [(set (match_operand:DI 0 "arm_low_register_operand" "=l") (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") (match_operand:SI 2 "register_operand" "r")]
