https://gcc.gnu.org/g:31b3fbffcdbe00dbf7717d18f487d77d3bfbaceb
commit 31b3fbffcdbe00dbf7717d18f487d77d3bfbaceb Author: Michael Meissner <[email protected]> Date: Wed Nov 12 22:48:47 2025 -0500 Revert changes Diff: --- gcc/config.gcc | 19 -- gcc/config/rs6000/float16.cc | 185 --------------- gcc/config/rs6000/float16.md | 458 +------------------------------------- gcc/config/rs6000/rs6000-call.cc | 34 +-- gcc/config/rs6000/rs6000-cpus.def | 13 +- gcc/config/rs6000/rs6000-protos.h | 13 -- gcc/config/rs6000/t-rs6000 | 4 - 7 files changed, 9 insertions(+), 717 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 9449d4adf136..205654a79985 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,6 @@ powerpc*-*-*) extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o" extra_objs="${extra_objs} rs6000-call.o rs6000-pcrel-opt.o" extra_objs="${extra_objs} rs6000-builtins.o rs6000-builtin.o" - extra_objs="${extra_objs} float16.o" extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h" extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h" extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h" @@ -5816,24 +5815,6 @@ case "${target}" in elif test x$with_long_double_format = xibm; then tm_defines="${tm_defines} TARGET_IEEEQUAD_DEFAULT=0" fi - - # Test if we should enable 16-bit floating point on the platforms - # where we can support __bfloat16 and _Float16. - if test x$with_powerpc_float16 = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=1" - - elif test x$with_powerpc_16bit_floating_point = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=0" - fi - - # Test if we should disable the warning about passing - # and returning 16-bit floating point values. - if test x$with_powerpc_float16_disable_warning = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=1" - - elif test x$with_powerpc_float16_disable_warning = xno; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=0" - fi ;; s390*-*-*) diff --git a/gcc/config/rs6000/float16.cc b/gcc/config/rs6000/float16.cc deleted file mode 100644 index 5274a0df962f..000000000000 --- a/gcc/config/rs6000/float16.cc +++ /dev/null @@ -1,185 +0,0 @@ -/* Subroutines for the C front end on the PowerPC architecture. - Copyright (C) 2002-2025 Free Software Foundation, Inc. - - Contributed by Zack Weinberg <[email protected]> - and Paolo Bonzini <[email protected]> - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -/* 16-bit floating point support. */ - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "backend.h" -#include "rtl.h" -#include "tree.h" -#include "memmodel.h" -#include "tm_p.h" -#include "stringpool.h" -#include "expmed.h" -#include "optabs.h" -#include "regs.h" -#include "insn-attr.h" -#include "flags.h" -#include "attribs.h" -#include "explow.h" -#include "expr.h" -#include "common/common-target.h" -#include "rs6000-internal.h" - -/* Expand a 16-bit vector operation: - - ICODE: Operation to perform. - RESULT: Result of the operation. - OP1: Input operand1. - OP2: Input operand2. - OP3: Input operand3 or NULL_RTX. - SUBTYPE: Describe the operation. */ - -void -fp16_vectorization (enum rtx_code icode, - rtx result, - rtx op1, - rtx op2, - rtx op3, - enum fp16_operation subtype) -{ - gcc_assert (can_create_pseudo_p ()); - - machine_mode result_mode = GET_MODE (result); - rtx op_orig[3] = { op1, op2, op3 }; - rtx op_hi[3]; - rtx op_lo[3]; - rtx result_hi; - rtx result_lo; - size_t n_opts; - - switch (subtype) - { - case FP16_BINARY: - n_opts = 2; - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - n_opts = 3; - break; - - default: - gcc_unreachable (); - } - - /* Allocate 2 temporaries for the results and the input operands. */ - result_hi = gen_reg_rtx (V4SFmode); - result_lo = gen_reg_rtx (V4SFmode); - - for (size_t i = 0; i < n_opts; i++) - { - gcc_assert (op_orig[i] != NULL_RTX); - op_hi[i] = gen_reg_rtx (V4SFmode); /* high register. */ - op_lo[i] = gen_reg_rtx (V4SFmode); /* low register. */ - - rtx interleave_hi = gen_reg_rtx (result_mode); - rtx interleave_lo = gen_reg_rtx (result_mode); - rtx orig = op_orig[i]; - - rs6000_expand_interleave (interleave_hi, orig, orig, !BYTES_BIG_ENDIAN); - rs6000_expand_interleave (interleave_lo, orig, orig, BYTES_BIG_ENDIAN); - - if (result_mode == V8HFmode) - { - emit_insn (gen_xvcvhpsp_v8hf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvhpsp_v8hf (op_lo[i], interleave_lo)); - } - - else if (result_mode == V8BFmode) - { - emit_insn (gen_xvcvbf16spn_v8bf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvbf16spn_v8bf (op_lo[i], interleave_lo)); - } - - else - gcc_unreachable (); - } - - /* Do 2 sets of V4SFmode operations. */ - switch (subtype) - { - case FP16_BINARY: - emit_insn (gen_rtx_SET (result_hi, - gen_rtx_fmt_ee (icode, V4SFmode, - op_hi[0], - op_hi[1]))); - - emit_insn (gen_rtx_SET (result_lo, - gen_rtx_fmt_ee (icode, V4SFmode, - op_lo[0], - op_lo[1]))); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - { - rtx op1_hi = op_hi[0]; - rtx op2_hi = op_hi[1]; - rtx op3_hi = op_hi[2]; - - rtx op1_lo = op_lo[0]; - rtx op2_lo = op_lo[1]; - rtx op3_lo = op_lo[2]; - - if (subtype == FP16_FMS || subtype == FP16_NFMS) - { - op3_hi = gen_rtx_NEG (V4SFmode, op3_hi); - op3_lo = gen_rtx_NEG (V4SFmode, op3_lo); - } - - rtx op_fma_hi = gen_rtx_FMA (V4SFmode, op1_hi, op2_hi, op3_hi); - rtx op_fma_lo = gen_rtx_FMA (V4SFmode, op1_lo, op2_lo, op3_lo); - - if (subtype == FP16_NFMA || subtype == FP16_NFMS) - { - op_fma_hi = gen_rtx_NEG (V4SFmode, op_fma_hi); - op_fma_lo = gen_rtx_NEG (V4SFmode, op_fma_lo); - } - - emit_insn (gen_rtx_SET (result_hi, op_fma_hi)); - emit_insn (gen_rtx_SET (result_lo, op_fma_lo)); - } - break; - - default: - gcc_unreachable (); - } - - /* Combine the 2 V4SFmode operations into one V8HFmode/V8BFmode vector. */ - if (result_mode == V8HFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8hf (result, result_hi, result_lo)); - - else if (result_mode == V8BFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8bf (result, result_hi, result_lo)); - - else - gcc_unreachable (); - - return; -} diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index b387f4dbbab8..6805cd994398 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -60,27 +60,12 @@ (V8BF "V4BF") (V8HF "V4HF")]) -;; Binary operators for bfloat16/float16 vectorization. -(define_code_iterator FP16_BINARY_OP [plus minus mult smax smin]) - -;; Standard names for the unary/binary/ternary operators -(define_code_attr fp16_names [(abs "abs") - (fma "fma") - (plus "add") - (minus "sub") - (mult "mul") - (neg "neg") - (smax "smax") - (smin "smin")]) - ;; UNSPEC constants (define_c_enum "unspec" [UNSPEC_FP16_SHIFT_LEFT_32BIT UNSPEC_CVT_FP16_TO_V4SF UNSPEC_XXSPLTW_FP16 - UNSPEC_XVCVSPBF16_BF - UNSPEC_XVCVSPHP_V8HF - UNSPEC_XVCVSPBF16_V8BF]) + UNSPEC_XVCVSPBF16_BF]) ;; _Float16 and __bfloat16 moves (define_expand "mov<mode>" @@ -522,444 +507,3 @@ emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp)); DONE; }) - -;; Negate 16-bit floating point by XOR with -0.0. - -(define_insn_and_split "neg<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (xor:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit floating point absolute value - -(define_insn_and_split "abs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (and:FP16 (match_dup 1) - (not:FP16 (match_dup 2))))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit negative floating point absolute value - -(define_insn_and_split "*nabs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (ior:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; Add logical operations for 16-bit floating point types that are used -;; for things like negate, abs, and negative abs. Possibly in the -;; future we might need logical operators for extracting exponents and -;; mantissas. -(define_expand "and<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "ior<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "xor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "nor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -(define_expand "andn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -(define_expand "eqv<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (not:FP16 - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; Rewrite nand into canonical form -(define_expand "nand<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; The canonical form is to have the negated element first, so we need to -;; reverse arguments. -(define_expand "iorn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -;; AND, IOR, and XOR insns. Unlike HImode operations prefer using -;; floating point/vector registers over GPRs. -(define_insn "*bool<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; ANDC, IORC, and EQV insns. -(define_insn "*boolc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r")) - (match_operand:FP16 1 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -(define_insn "*boolc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; NOR and NAND insns. -(define_insn "*boolcc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(not:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,r")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; Add vectorization support for 16-bit floating point. - -;; Binary operators being vectorized. -(define_insn_and_split "<fp16_names><mode>3" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (FP16_BINARY_OP:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (<CODE>, operands[0], operands[1], operands[2], NULL_RTX, - FP16_BINARY); - DONE; -}) - -;; FMA operations being vectorized. -(define_insn_and_split "fma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*fms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*nfma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*nfms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand")))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -;; Vector Pack support. - -(define_expand "vec_pack_trunc_v4sf_v8hf" - [(match_operand:V8HF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8HFmode); - rtx r2 = gen_reg_rtx (V8HFmode); - - emit_insn (gen_xvcvsphp_v8hf (r1, operands[1])); - emit_insn (gen_xvcvsphp_v8hf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -(define_expand "vec_pack_trunc_v4sf_v8bf" - [(match_operand:V8BF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8BFmode); - rtx r2 = gen_reg_rtx (V8BFmode); - - emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1])); - emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -;; Unfortunately the machine independent code assumes there is only one -;; 16-bit floating point type. This means we have to choose whether to -;; support packing _Float16 or __bfloat16. It looks like __bfloat16 is -;; more popular, so we choose __bfloat16 to be the default. - -(define_expand "vec_pack_trunc_v4sf" - [(match_operand:V8BF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8BFmode); - rtx r2 = gen_reg_rtx (V8BFmode); - - emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1])); - emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -;; Used for vector conversion to _Float16 -(define_insn "xvcvsphp_v8hf" - [(set (match_operand:V8HF 0 "vsx_register_operand" "=wa") - (unspec:V8HF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPHP_V8HF))] - "TARGET_FLOAT16_HW" - "xvcvsphp %x0,%x1" -[(set_attr "type" "vecfloat")]) - -;; Used for vector conversion to __bfloat16 -(define_insn "xvcvspbf16_v8bf" - [(set (match_operand:V8BF 0 "vsx_register_operand" "=wa") - (unspec:V8BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_V8BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Vector unpack support. Given the name is for the type being -;; unpacked, we can unpack both __bfloat16 and _Float16. - -;; Unpack vector _Float16 -(define_expand "vec_unpacks_hi_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from _Float16 -(define_insn "xvcvhpsp_v8hf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8HF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvhpsp %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Unpack vector __bfloat16 -(define_expand "vec_unpacks_hi_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from __bfloat16 -(define_insn "xvcvbf16spn_v8bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8BF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index 4f6c8166095d..1c5bec25ecbe 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -686,27 +686,17 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, " to enable them", "-maltivec"); } -#if !POWERPC_FLOAT16_DISABLE_WARNING /* Warn that __bfloat16 and _Float16 might be returned differently in the future. The issue is currently 16-bit floating point is returned in floating point register #1 in 16-bit format. We may or may not want to return it as a scalar 64-bit value. */ if (fntype && warn_psabi && !cum->libcall) { - static bool warned_about_float16_return = false; - - if (!warned_about_float16_return) - { - machine_mode ret_mode = TYPE_MODE (TREE_TYPE (fntype)); - - warned_about_float16_return = true; - if (ret_mode == BFmode || ret_mode == HFmode) - warning (OPT_Wpsabi, - "%s might be returned differently in the future", - ret_mode == BFmode ? "__bfloat16" : "_Float16"); - } + machine_mode ret_mode = TYPE_MODE (TREE_TYPE (fntype)); + if (ret_mode == BFmode || ret_mode == HFmode) + warning (OPT_Wpsabi, "%s might be returned differently in the future", + ret_mode == BFmode ? "__bfloat16" : "_Float16"); } -#endif } @@ -1665,23 +1655,13 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) return NULL_RTX; } -#if !POWERPC_FLOAT16_DISABLE_WARNING /* Warn that _Float16 and __bfloat16 might be passed differently in the future. The issue is currently 16-bit floating point values are passed in floating point registers in the native 16-bit format. We may or may not want to pass the value it as a scalar 64-bit value. */ - if (warn_psabi && !cum->libcall && FP16_SCALAR_MODE_P (mode)) - { - static bool warned_about_float16_call = false; - - if (!warned_about_float16_call) - { - warned_about_float16_call = true; - warning (OPT_Wpsabi, "%s might be passed differently in the future", - mode == BFmode ? "__bfloat16" : "_Float16"); - } - } -#endif + if (warn_psabi && !cum->libcall && (mode == BFmode || mode == HFmode)) + warning (OPT_Wpsabi, "%s might be passed differently in the future", + mode == BFmode ? "__bfloat16" : "_Float16"); /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 uses to say fp args were passed in registers. diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 3e7c95da7b4a..c03b069b779b 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -43,15 +43,6 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) -/* Determine whether to enable 16-bit floating point types on power8 systems - and above. */ -#if POWERPC_FLOAT16_DEFAULT -#define TARGET_16BIT_FLOATING_POINT OPTION_MASK_FLOAT16 - -#else -#define TARGET_16BIT_FLOATING_POINT 0 -#endif - /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ @@ -61,8 +52,7 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | TARGET_16BIT_FLOATING_POINT) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ @@ -141,7 +131,6 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ - | OPTION_MASK_FLOAT16 \ | OPTION_MASK_FPRND \ | OPTION_MASK_FUTURE \ | OPTION_MASK_POWER10 \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index dd5fcd69e836..d29081837b35 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -258,19 +258,6 @@ extern bool vec_const_128bit_to_bytes (rtx, machine_mode, extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); - -/* From float16.cc. */ -/* Optimize bfloat16 and float16 operations. */ -enum fp16_operation { - FP16_BINARY, /* Bfloat16/float16 binary op. */ - FP16_FMA, /* (a * b) + c. */ - FP16_FMS, /* (a * b) - c. */ - FP16_NFMA, /* - ((a * b) + c). */ - FP16_NFMS /* - ((a * b) - c). */ -}; - -extern void fp16_vectorization (enum rtx_code, rtx, rtx, rtx, rtx, - enum fp16_operation); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index c8f19865311c..a5d1c27424f3 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -87,10 +87,6 @@ rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.cc rs6000-builtins.h $(COMPILE) $< $(POSTCOMPILE) -float16.o: $(srcdir)/config/rs6000/float16.cc - $(COMPILE) $< - $(POSTCOMPILE) - #$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl # $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md
