https://gcc.gnu.org/g:6947098a34ccc2f64ff52de88a136bc438091c10
commit r16-5190-g6947098a34ccc2f64ff52de88a136bc438091c10 Author: Kuan-Lin Chen <[email protected]> Date: Wed Nov 12 10:44:26 2025 +0800 RISC-V: Add Andes 25 series pipeline description. gcc/ChangeLog: * config/riscv/andes-25-series.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-25-series. (RISCV_CORE): Add Andes 25-series cpu list. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add andes_25_series_. * config/riscv/riscv.cc: Add andes_25_tune_info. * config/riscv/riscv.md: Add andes_25. * doc/riscv-mcpu.texi: Regenerated for Andes cpu list. * doc/riscv-mtune.texi: Regenerated for andes-25-series. Diff: --- gcc/config/riscv/andes-25-series.md | 322 ++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-cores.def | 10 ++ gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 24 +++ gcc/config/riscv/riscv.md | 4 +- gcc/doc/riscv-mcpu.texi | 16 +- gcc/doc/riscv-mtune.texi | 2 + 7 files changed, 377 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/andes-25-series.md b/gcc/config/riscv/andes-25-series.md new file mode 100644 index 000000000000..ef1a926de864 --- /dev/null +++ b/gcc/config/riscv/andes-25-series.md @@ -0,0 +1,322 @@ +;; DFA-based pipeline description for Andes 25 series. +;; +;; Copyright (C) 2025 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "andes_25_arch, andes_25_vector") + +;; Integer pipeline +(define_cpu_unit "andes_25_pipe" "andes_25_arch") +;; Division operation unit +(define_cpu_unit "andes_25_mdu" "andes_25_arch") +;; Floating point units +(define_cpu_unit "andes_25_fpu, andes_25_fpu_eu" "andes_25_arch") + +;; Vector execution unit. +(define_cpu_unit "andes_25_vpu_lsu, andes_25_vpu_alu, andes_25_vpu_mac, + andes_25_vpu_msk, andes_25_vpu_div, andes_25_vpu_fmac, + andes_25_vpu_fmis, andes_25_vpu_perm, andes_25_vpu_pipe" + "andes_25_vector") + +;; andes 25 series unsupported insns are mapped to dummies reservations +(define_reservation "andes_25_dummies" + "andes_25_pipe | andes_25_mdu | andes_25_fpu" +) + +;; andes 25 series vector unsupported insns are mapped to dummies reservations +(define_reservation "andes_25_vector_dummies" + "andes_25_vpu_lsu | andes_25_vpu_alu | andes_25_vpu_mac | andes_25_vpu_msk | + andes_25_vpu_div | andes_25_vpu_fmac | andes_25_vpu_fmis | + andes_25_vpu_perm | andes_25_vpu_pipe" +) + +(define_reservation "andes_25_fpu_arith" + "(andes_25_pipe + andes_25_fpu), andes_25_fpu_eu * 2") + +(define_reservation "andes_25_fpu_pipe" + "andes_25_pipe + andes_25_fpu") + +(define_insn_reservation "andes_25_alu_insn" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "unknown,const,arith,shift,slt,multi,nop,logical,move, + auipc,atomic")) + "andes_25_pipe") + +(define_insn_reservation "andes_25_load_wd" 2 + (and (eq_attr "tune" "andes_25_series") + (and (eq_attr "type" "load") + (not (eq_attr "mode" "QI,HI")))) + "andes_25_pipe") + +(define_insn_reservation "andes_25_load_bh" 3 + (and (eq_attr "tune" "andes_25_series") + (and (eq_attr "type" "load") + (eq_attr "mode" "QI,HI"))) + "andes_25_pipe") + +(define_insn_reservation "andes_25_store" 0 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "store")) + "andes_25_pipe") + +(define_insn_reservation "andes_25_branch" 0 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "branch,jump,call,jalr,trap,ret")) + "andes_25_pipe") + +(define_insn_reservation "andes_25_imul" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "imul")) + "andes_25_pipe") + +(define_insn_reservation "andes_25_idivsi" 38 + (and (eq_attr "tune" "andes_25_series") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "andes_25_pipe, andes_25_mdu * 34") + +(define_insn_reservation "andes_25_idivdi" 70 + (and (eq_attr "tune" "andes_25_series") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "andes_25_pipe, andes_25_mdu * 66") + +(define_insn_reservation "andes_25_xfer" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "mfc,mtc")) + "andes_25_pipe") + +(define_insn_reservation "andes_25_fpu_alu" 5 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fadd")) + "andes_25_fpu_arith") + +(define_insn_reservation "andes_25_fpu_mul" 5 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fmul")) + "andes_25_fpu_arith") + +(define_insn_reservation "andes_25_fpu_mac" 5 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fmadd")) + "andes_25_fpu_arith") + +(define_insn_reservation "andes_25_fpu_div" 33 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fdiv")) + "andes_25_fpu_arith, andes_25_fpu_eu * 27") + +(define_insn_reservation "andes_25_fpu_sqrt" 33 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fsqrt")) + "andes_25_fpu_arith, andes_25_fpu_eu * 27") + +(define_insn_reservation "andes_25_fpu_move" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fmove,mtc,mfc")) + "andes_25_fpu_pipe") + +(define_insn_reservation "andes_25_fpu_cmp" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fcmp")) + "andes_25_fpu_pipe") + +(define_insn_reservation "andes_25_fpu_cvt" 6 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i")) + "andes_25_fpu_arith, andes_25_fpu_eu") + +(define_insn_reservation "andes_25_fpu_load" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fpload")) + "andes_25_fpu_pipe") + +(define_insn_reservation "andes_25_fpu_store" 0 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "fpstore")) + "andes_25_fpu_pipe") + +(define_insn_reservation "andes_25_bitmanip" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "bitmanip")) + "andes_25_pipe") + +;; Vector pipeline. + +(define_insn_reservation "andes_25_vload" 5 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vlde,vldm,vlds,vldff,vldr")) + "(andes_25_vpu_pipe + andes_25_vpu_lsu)*3") + +(define_insn_reservation "andes_25_index_vload" 8 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vldux,vldox")) + "(andes_25_vpu_pipe + andes_25_vpu_lsu)*3") + +(define_insn_reservation "andes_25_seg_vload" 16 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff")) + "(andes_25_vpu_pipe + andes_25_vpu_lsu)*3") + +(define_insn_reservation "andes_25_vstore" 0 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr,vssegte,\ + vssegts,vssegtux,vssegtox")) + "(andes_25_vpu_pipe + andes_25_vpu_lsu)*3") + +(define_insn_reservation "andes_25_vialu" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vialu,vicalu,vshift,viminmax,vicmp,vimov,\ + vsalu,vaalu,vmov,vector,vimerge")) + "andes_25_vpu_pipe + andes_25_vpu_alu") + +(define_insn_reservation "andes_25_widen_vialu" 2 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "viwalu, vext, vsshift")) + "andes_25_vpu_pipe + andes_25_vpu_alu") + +(define_insn_reservation "andes_25_narrow_vialu" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vnshift,vnclip")) + "andes_25_vpu_pipe + andes_25_vpu_alu") + +(define_insn_reservation "andes_25_vimul" 2 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vimul,vimuladd,vsmul")) + "andes_25_vpu_pipe + andes_25_vpu_mac") + +(define_insn_reservation "andes_25_widen_vimul" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "viwmul,viwmuladd")) + "andes_25_vpu_pipe + andes_25_vpu_mac") + +(define_insn_reservation "andes_25_vperm" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vslideup,vslidedown,vislide1up,vislide1down,\ + vfslide1up,vfslide1down,vgather")) + "andes_25_vpu_pipe + andes_25_vpu_perm") + +(define_insn_reservation "andes_25_vcompress" 4 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vcompress")) + "andes_25_vpu_pipe + andes_25_vpu_perm") + +(define_insn_reservation "andes_25_vmovv" 7 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vimovvx,vfmovvf")) + "(andes_25_vpu_pipe + andes_25_vpu_perm)*5") + +(define_insn_reservation "andes_25_vmovx" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vimovxv,vfmovfv,vfmov")) + "andes_25_vpu_pipe + andes_25_vpu_perm") + +(define_insn_reservation "andes_25_vreduction" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vired,viwred")) + "andes_25_vpu_pipe + andes_25_vpu_alu*5") + +(define_insn_reservation "andes_25_vidiv" 35 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vidiv")) + "andes_25_vpu_pipe + andes_25_vpu_div*34") + +(define_insn_reservation "andes_25_vmask_2" 2 + (eq_attr "type" "vmalu,vmsfs") + "andes_25_vpu_pipe + andes_25_vpu_msk") + +(define_insn_reservation "andes_25_vmask_3" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vmiota,vmidx")) + "andes_25_vpu_pipe + andes_25_vpu_msk") + +(define_insn_reservation "andes_25_vpopc" 6 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vmpop")) + "andes_25_vpu_pipe + andes_25_vpu_msk") + +(define_insn_reservation "andes_25_vffs" 7 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vmffs")) + "andes_25_vpu_pipe + andes_25_vpu_msk") + +(define_insn_reservation "andes_25_vfadd" 4 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfalu,vfwalu,vfmul,vfwmul,vfmuladd,\ + vfwmuladd")) + "andes_25_vpu_pipe + andes_25_vpu_fmac") + +(define_insn_reservation "andes_25_vfdiv" 39 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfdiv,vfsqrt")) + "andes_25_vpu_pipe + andes_25_vpu_div*19") + +(define_insn_reservation "andes_25_vfmis" 2 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfminmax,vfcmp,vfsgnj,vfclass,vfmerge")) + "andes_25_vpu_pipe + andes_25_vpu_fmis") + +(define_insn_reservation "andes_25_vfrecp" 3 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfrecp")) + "andes_25_vpu_pipe + andes_25_vpu_div") + +(define_insn_reservation "andes_25_vfcvt" 2 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfcvtitof,vfcvtftoi")) + "andes_25_vpu_pipe + andes_25_vpu_fmis") + +(define_insn_reservation "andes_25_widen_vfcvt" 5 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfwcvtbf16")) + "andes_25_vpu_pipe + andes_25_vpu_fmis") + +(define_insn_reservation "andes_25_narrow_vfcvt" 4 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfncvtitof,vfncvtftoi,vfncvtftof,vfncvtbf16")) + "andes_25_vpu_pipe + andes_25_vpu_fmis") + +(define_insn_reservation "andes_25_vfreduction" 6 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vfredu,vfwredu,vfredo,vfwredo")) + "andes_25_vpu_pipe + andes_25_vpu_fmac*24") + +(define_insn_reservation "andes_25_vesetvl" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vsetvl,vsetvl_pre")) + "andes_25_vpu_pipe") + +(define_insn_reservation "andes_25_vcsr" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "wrvxrm,wrfrm,rdvlenb,rdvl")) + "andes_25_vpu_pipe") + +(define_insn_reservation "andes_25_unknown" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "ghost,cpop,clz,ctz,zicond,mvpair,sfb_alu,minu,maxu, + min,max,clmul,rotate,crypto,condmove,rdfrm")) + "andes_25_dummies") + +(define_insn_reservation "andes_25_vector_unknown" 1 + (and (eq_attr "tune" "andes_25_series") + (eq_attr "type" "vclz,vror,vsha2ch,vsm4k,vaesef,vghsh,vsm4r,vsm3c, + vaeskf1,vandn,vaesdm,vclmul,vclmulh,vrol,vcpop,vbrev8, + vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8, + vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16, + sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip")) + "andes_25_vector_dummies") diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index cc9d5c03cb8c..19d27b8998f7 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -53,6 +53,7 @@ RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info) +RISCV_TUNE("andes-25-series", andes_25_series, andes_25_tune_info) #undef RISCV_TUNE @@ -171,4 +172,13 @@ RISCV_CORE("xiangshan-kunminghu", "rv64imafdcbvh_sdtrig_sha_shcounterenw_" RISCV_CORE("mips-p8700", "rv64imfd_zicsr_zifencei_zalrsc_zba_zbb", "mips-p8700") + +RISCV_CORE("andes-n22", "rv32imc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-n25", "rv32imc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-a25", "rv32imafdc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-nx25", "rv64imc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-ax25", "rv64imafdc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-a27", "rv32imafdc_zicsr_zifencei_xandesperf", "andes-25-series") +RISCV_CORE("andes-ax27", "rv64imafdc_zicsr_zifencei_xandesperf", "andes-25-series") + #undef RISCV_CORE diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4e4e9d8930e2..95c032d33d23 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -61,6 +61,7 @@ enum riscv_microarchitecture_type { generic_ooo, mips_p8700, tt_ascalon_d8, + andes_25_series, }; extern enum riscv_microarchitecture_type riscv_microarchitecture; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2b2fada592f0..5bb557faf657 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -735,6 +735,30 @@ static const struct riscv_tune_param mips_p8700_tune_info = { true, /* prefer-agnostic. */ }; +/* Costs to use when optimizing for Andes 25 series. */ +static const struct riscv_tune_param andes_25_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ + {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */ + {COSTS_N_INSNS (24), COSTS_N_INSNS (24)}, /* int_div */ + 1, /* issue_rate */ + 3, /* branch_cost */ + 3, /* memory_cost */ + 8, /* fmv_cost */ + false, /* slow_unaligned_access */ + false, /* vector_unaligned_access */ + true, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + false, /* use_zero_stride_load */ + false, /* speculative_sched_vsetvl */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ + NULL, /* function_align */ + NULL, /* jump_align */ + NULL, /* loop_align */ +}; + static bool riscv_avoid_shrink_wrapping_separate (); static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1ec15da2e77e..d179f1f49c89 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -672,7 +672,8 @@ ;; Microarchitectures we know how to tune for. ;; Keep this in sync with enum riscv_microarchitecture. (define_attr "tune" - "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,tt_ascalon_d8" + "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700, + tt_ascalon_d8,andes_25_series" (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) ;; Describe a user's asm statement. @@ -5017,3 +5018,4 @@ (include "generic-vector-ooo.md") (include "generic-ooo.md") (include "tt-ascalon-d8.md") +(include "andes-25-series.md") diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi index 6753e510eb61..f79edfb837c8 100644 --- a/gcc/doc/riscv-mcpu.texi +++ b/gcc/doc/riscv-mcpu.texi @@ -66,4 +66,18 @@ by particular CPU name. Permissible values for this option are: @samp{xiangshan-kunminghu}, -@samp{mips-p8700}. +@samp{mips-p8700}, + +@samp{andes-n22}, + +@samp{andes-n25}, + +@samp{andes-a25}, + +@samp{andes-nx25}, + +@samp{andes-ax25}, + +@samp{andes-a27}, + +@samp{andes-ax27}. diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi index a2a4d3e77dbb..cf713670fd69 100644 --- a/gcc/doc/riscv-mtune.texi +++ b/gcc/doc/riscv-mtune.texi @@ -56,4 +56,6 @@ particular CPU name. Permissible values for this option are: @samp{mips-p8700}, +@samp{andes-25-series}, + and all valid options for @option{-mcpu=}.
