https://gcc.gnu.org/g:cd279ded4e5c617c7f13ed29a81f59824607725a
commit cd279ded4e5c617c7f13ed29a81f59824607725a Author: Pan Li <[email protected]> Date: Fri Sep 26 23:12:27 2025 +0800 ISC-V: Add test for vec_duplicate + vwaddu.wv signed combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vwaddu.wv combine to vwaddu.wx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwaddu.wx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test helper macros and data. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_wx_run.h: New test. * gcc.target/riscv/rvv/autovec/vx_vf/wx_vwaddu-run-1-u64.c: New test. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit ddd69ed8f85e7ce488a8c7638cd3c958938dfa33) Diff: --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 3 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 3 +- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h | 18 +++++ .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 77 +++++++++++++++++++++- .../riscv/rvv/autovec/vx_vf/vx_widen_wx_run.h | 27 ++++++++ .../riscv/rvv/autovec/vx_vf/wx_vwaddu-run-1-u64.c | 18 +++++ 13 files changed, 149 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index c86461beadf2..76ef2d3f0206 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -12,7 +12,7 @@ TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vadd.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vand.vx} 1 } } */ @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 90de1974ab1f..55fa57dec35d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -12,7 +12,7 @@ TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vadd.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vand.vx} 1 } } */ @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 522ddd19ccd4..d5176834494e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -35,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 6ea17bb83d9b..a234505ce81c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 8b8fba54b72a..a46c874d0a44 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 6f66de906a29..94ce774fc2aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index cd129f1f50ea..a1278cec61d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 48aeed71eb9c..910fa6e31580 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index b88c350acf3e..9ce0211603ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -32,3 +32,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ /* { dg-final { scan-assembler-not {vwmulu.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.wx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h index 998c05961ab0..03fba3c2a0c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -28,9 +28,27 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ #define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \ RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) +#define DEF_VX_WIDEN_BINARY_CASE_1(WT, NT, OP, NAME) \ +void \ +test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT * restrict vd, \ + WT * restrict vs2, \ + NT rs1, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + vd[i] = vs2[i] OP (WT)rs1; \ +} + +#define DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, OP, NAME) \ + DEF_VX_WIDEN_BINARY_CASE_1(WT, NT, OP, NAME) +#define RUN_VX_WIDEN_BINARY_CASE_1(WT, NT, NAME, vd, vs2, rs1, n) \ + test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1(vd, vs2, rs1, n) +#define RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \ + RUN_VX_WIDEN_BINARY_CASE_1(WT, NT, NAME, vd, vs2, rs1, n) + #define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \ + DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, add) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h index 5b49083abe72..faf46a81e6ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -4,7 +4,7 @@ #define N 16 #define DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) \ - binary_widen_##WT##_##NT##_##NAME##_s + binary_widen_##WT##_##NT##_##NAME##_s_0 #define DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) \ DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) @@ -14,7 +14,7 @@ DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) #define DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) \ - binary_widen_##WT##_##NT##_##NAME##_data + binary_widen_##WT##_##NT##_##NAME##_data_0 #define DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) \ DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) @@ -24,6 +24,27 @@ #define DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(WT, NT, NAME) \ DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_1_NAME(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_s_1 +#define DEF_BINARY_WIDEN_STRUCT_1_NAME_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_NAME(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_1_TYPE(WT, NT, NAME) \ + struct DEF_BINARY_WIDEN_STRUCT_1_NAME_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_TYPE(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_1_VAR(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_data_1 +#define DEF_BINARY_WIDEN_STRUCT_1_VAR_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_VAR(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_1_DECL(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_VAR_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_DECL(WT, NT, NAME) + #define DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) \ DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ { \ @@ -39,6 +60,19 @@ DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub) DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul) +#define DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) \ + { \ + WT vs2[N]; \ + NT rs1; \ + WT expect[N]; \ + WT vd[N]; \ + }; +#define DEF_BINARY_WIDEN_STRUCT_1_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME) + +DEF_BINARY_WIDEN_STRUCT_1_WRAP(uint64_t, uint32_t, add) + DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { { /* vs2 */ @@ -156,4 +190,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, mul)[] = { }, }; +DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, add)[] = { + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483649, 2147483649, 2147483649, 2147483649, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 2147483648, 2147483648, 2147483648, 2147483648, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + }, + }, + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull, + 8589934591ull, 8589934591ull, 8589934591ull, 8589934591ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_wx_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_wx_run.h new file mode 100644 index 000000000000..6edd48605044 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_wx_run.h @@ -0,0 +1,27 @@ +#ifndef HAVE_DEFINED_WX_WIDEN_RUN_H +#define HAVE_DEFINED_WX_WIDEN_RUN_H + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + DATA_TYPE *data = &TEST_DATA[i]; + WT *vs2 = data->vs2; + NT rs1 = data->rs1; + WT *expect = data->expect; + WT *vd = data->vd; + + TEST_RUN (WT, NT, NAME, vd, vs2, rs1, N); + + for (k = 0; k < N; k++) + if (vd[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwaddu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwaddu-run-1-u64.c new file mode 100644 index 000000000000..fe0ea7cb3c93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/wx_vwaddu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME add +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_1_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_wx_run.h"
